search for: allowsunalignedmem

...lt;dpeixott at codeaurora.org> wrote: > >> Hi Pete, >> >> We ran into the same issue with generating vector loads/stores for >> vectors with less than word alignment. It seems we took a similar >> approach to solving the problem by modifying the logic in > allowsUnalignedMemoryAccesses. >> >> As you and Jim mentioned, it looks like the vld1/vst1 instructions >> should support element aligned access for any armv7 implementation >> (I'm looking at Table A3-1 ARM Architecture Reference Manual - ARM DDI > 0406C). >> >> Right n...

..., at 2:48 PM, David Peixotto <dpeixott at codeaurora.org> wrote: > Hi Pete, > > We ran into the same issue with generating vector loads/stores for > vectors with less than word alignment. It seems we took a similar > approach to solving the problem by modifying the logic in allowsUnalignedMemoryAccesses. > > As you and Jim mentioned, it looks like the vld1/vst1 instructions > should support element aligned access for any armv7 implementation > (I'm looking at Table A3-1 ARM Architecture Reference Manual - ARM DDI 0406C). > > Right now I do not think we have the...

...12, at 2:48 PM, David Peixotto <dpeixott at codeaurora.org> wrote: > Hi Pete, > > We ran into the same issue with generating vector loads/stores for vectors > with less than word alignment. It seems we took a similar approach to > solving the problem by modifying the logic in allowsUnalignedMemoryAccesses. > > As you and Jim mentioned, it looks like the vld1/vst1 instructions should > support element aligned access for any armv7 implementation (I'm looking at > Table A3-1 ARM Architecture Reference Manual - ARM DDI 0406C). > > Right now I do not think we have the c...

...t; wrote: > > > >> Hi Pete, > >> > >> We ran into the same issue with generating vector loads/stores for > >> vectors with less than word alignment. It seems we took a similar > >> approach to solving the problem by modifying the logic in > > allowsUnalignedMemoryAccesses. > >> > >> As you and Jim mentioned, it looks like the vld1/vst1 instructions > >> should support element aligned access for any armv7 implementation > >> (I'm looking at Table A3-1 ARM Architecture Reference Manual - ARM > >> DDI > &gt...

Hi Pete, We ran into the same issue with generating vector loads/stores for vectors with less than word alignment. It seems we took a similar approach to solving the problem by modifying the logic in allowsUnalignedMemoryAccesses. As you and Jim mentioned, it looks like the vld1/vst1 instructions should support element aligned access for any armv7 implementation (I'm looking at Table A3-1 ARM Architecture Reference Manual - ARM DDI 0406C). Right now I do not think we have the correct code setup in ARMSubtar...

...es when NEON is available, but can't use unaligned accesses generally speaking? A new field in ARMSubtarget? Should the -arm-strict-align flag force expansion even on unaligned vector loads/stores? We got this working by adding a field to ARMSubtarget and changing logic in ARMTargetLowering::allowsUnalignedMemoryAccesses, but I am admittedly not entirely sure of the downstream consequences of this, as we don't allow unaligned access generally. Pete On 09/05/2012 04:58 PM, Jim Grosbach wrote: > Hmmm. Well, it's entirely possible that it's LLVM that's confused about the alignment req...

VLD1 expects a 64-bit aligned address unless the target explicitly days that unaligned loads are OK. For your situation, either the subtarget should set AllowsUnalignedMem to true (if that's accurate), or the load address should be made 64-bit aligned. -Jim On Sep 5, 2012, at 2:42 PM, Peter Couperus <peter.couperus at st.com> wrote: > Hello all, > > I am a first time writer here, but am a happy LLVM tinkerer. It is a pleasure to use :). > W...

Hello all, I am a first time writer here, but am a happy LLVM tinkerer. It is a pleasure to use :). We have come across some sub-optimal behavior when LLVM lowers loads for vectors with small integers, i.e. load <4 x i16>* %a, align 2, using a sequence of scalar loads rather than a single vld1 on armv7 linux with NEON. Looking at the code in svn, it appears the ARM backend is capable of

...2-byte aligned data. Is this not a guarantee across armv7/armv7a generally? Pete On 09/05/2012 03:15 PM, Jim Grosbach wrote: > VLD1 expects a 64-bit aligned address unless the target explicitly days that unaligned loads are OK. > > For your situation, either the subtarget should set AllowsUnalignedMem to true (if that's accurate), or the load address should be made 64-bit aligned. > > -Jim > > On Sep 5, 2012, at 2:42 PM, Peter Couperus<peter.couperus at st.com> wrote: > >> Hello all, >> >> I am a first time writer here, but am a happy LLVM tinkerer. I...

...cross armv7/armv7a generally? > > Pete > > > > > On 09/05/2012 03:15 PM, Jim Grosbach wrote: >> VLD1 expects a 64-bit aligned address unless the target explicitly days that unaligned loads are OK. >> >> For your situation, either the subtarget should set AllowsUnalignedMem to true (if that's accurate), or the load address should be made 64-bit aligned. >> >> -Jim >> >> On Sep 5, 2012, at 2:42 PM, Peter Couperus<peter.couperus at st.com> wrote: >> >>> Hello all, >>> >>> I am a first time writer he...