search for: allocatableregs_

...le by RA. A copy instruction: <regclass2 dst> = <regclass1 src> where src was allocated to register A will make dst be allocated also to A, even when it was defined as not allocatable in .td files. This is due to the checking in RegAllocLinearScan:1004 if (Reg && allocatableRegs_[Reg] && RC->contains(Reg)) mri_->setRegAllocationHint(cur->reg, 0, Reg); where "allocatableRegs_" is calculated during pass init, and ignores register class. I think this should be changed to: if (Reg && (tri_->getAllocatableSet(*mf_...

...Reg(PhysReg); for (const unsigned *AS = tri_->getAliasSet(PhysReg); *AS; ++AS) // If there are registers which alias PhysReg, but which are not a // sub-register of the chosen representative super register. Assert // since we can't handle it yet. assert(*AS == SpillReg || !allocatableRegs_[*AS] || tri_->isSuperRegister(*AS, SpillReg)); The test also asserts on trunk, though with an error about running out of registers. I am working to file a bug. I am also going to try 2.6. Any hints on what might be going on? -Dave

Roman Levenstein wrote: > Hi again, > > Now, after I fixed the graph coloring regalloc bug that was triggered > by the ARM target, I continue testing and found another bug, this time > on the XCore target. First I thought that it is again specific to my > register allocator, but it seems to be trigerred also by LLVM's > linearscan register allocator. > > I don't

.../// the register. Returns the virtual register. unsigned LiveIntervals::getReMatImplicitUse(const LiveInterval &li, MachineInstr *MI) const { But down in the code we have this: if (TargetRegisterInfo::isPhysicalRegister(Reg) && !allocatableRegs_[Reg]) continue; // FIXME: For now, only remat MI with at most one register operand. assert(!RegOp && "Can't rematerialize instruction with multiple register operand!"); RegOp = MO.getReg(); #ifndef NDEBUG break; #endif So if Reg is an allocata...

...> --- lib/CodeGen/LiveIntervalAnalysis.cpp (revision 60478) +++ lib/ > CodeGen/LiveIntervalAnalysis.cpp (working copy) @@ -820,6 +820,9 @@ > unsigned Reg = MO.getReg(); if (Reg == 0 || Reg == li.reg) continue; > + if (TargetRegisterInfo::isPhysicalRegister(Reg) && + ! > allocatableRegs_[Reg]) + continue; // FIXME: For now, only remat MI > with at most one register operand. assert(!RegOp && "Can't > rematerialize instruction with multiple register operand!"); > _______________________________________________ > LLVM Developers mailing list >...

Hi again, Now, after I fixed the graph coloring regalloc bug that was triggered by the ARM target, I continue testing and found another bug, this time on the XCore target. First I thought that it is again specific to my register allocator, but it seems to be trigerred also by LLVM's linearscan register allocator. I don't know if the XCore target is stable enough in LLVM, or may be I