Displaying 7 results from an estimated 7 matches for "alloc_temp".
2009 May 06
2
nv50: shader generation patches
Hi ! I've been trying to improve NV50 shader generation a bit the last couple of weeks, so here is
what I've produced. I don't know if it's usable for you or just a pile of horrible hacks, but at
least it makes some mesa demos render more correcly, p.e. the teapot (aside from mip-mapping issues
of the floor texture), arbfplight, and I think the gears also didn't appear as they
2009 Jun 24
0
[PATCH] nv50: fix previous patches
...c, fcrd, r_usage[1],
&mid, &aid, &oid);
pc->p->cfg.fp.regs[1] |= (mask << 24);
pc->p->cfg.fp.map[0] += 0x04040404 * fcrd;
+ oid = 0;
}
/* should do MAD fcrd.xy, fcrd, SOME_CONST, fcrd */
if (perspect_loads) {
pc->iv_p = alloc_temp(pc, NULL);
-
- if (!(pc->p->cfg.fp.regs[1] & 0x08000000)) {
- pc->p->cfg.fp.regs[1] |= 0x08000000;
+ pc->iv_p->rhw = aid - 1;
+ if (!(pc->p->cfg.fp.regs[1] & (1 << 27)))
pc->iv_p->rhw = aid++;
- emit_interp(pc, pc->iv_p, NULL,
-...
2009 Sep 12
0
[PATCH 10/13] nv50: proper linkage between VP and FP
...for (c = 0, n = i * 4; c < 4; c++, n++) {
- oid = (*p_oid)++;
+ ppiv = (mode & INTERP_CENTROID) ? &pc->iv_c : &pc->iv_p;
+ iv = *ppiv;
- if (!pc->attr[n].acc)
- continue;
- mask |= (1 << c);
+ if ((mode & INTERP_PERSPECTIVE) && !iv) {
+ iv = *ppiv = alloc_temp(pc, NULL);
+ iv->rhw = popcnt4(pc->p->cfg.regs[1] >> 24) - 1;
- alloc_reg(pc, &pc->attr[n]);
+ emit_interp(pc, iv, NULL, mode & INTERP_CENTROID);
+ emit_flop(pc, 0, iv, iv);
- pc->attr[n].rhw = (*aid)++;
- emit_interp(pc, &pc->attr[n], iv, pc->interp...
2009 Sep 10
0
[PATCH 06/13] nv50: handle SEQ, SGT, SLE, SNE opcodes
...4, 2, 6, 1, 5, 3, 7 };
struct nv50_reg *rdst;
- assert(c_op <= 7);
+ assert(ccode < 16);
if (check_swap_src_0_1(pc, &src0, &src1))
- c_op = inv_cop[c_op];
+ ccode = ccode ^ 0x7;
rdst = dst;
- if (dst->type != P_TEMP)
+ if (dst && dst->type != P_TEMP)
dst = alloc_temp(pc, NULL);
/* set.u32 */
set_long(pc, e);
e->inst[0] |= 0xb0000000;
- e->inst[1] |= (3 << 29);
- e->inst[1] |= (c_op << 14);
- /*XXX: breaks things, .u32 by default?
- * decuda will disasm as .u16 and use .lo/.hi regs, but this
- * doesn't seem to match wh...
2009 Sep 10
0
[PATCH 02/13] nv50: add functions for swizzle resolution
...if (!dst[c] || dst[c]->type != P_TEMP)
- continue;
-
- for (i = c + 1; i < 4; i++) {
- if (dst[c] == src[0][i] ||
- dst[c] == src[1][i] ||
- dst[c] == src[2][i])
- break;
- }
- if (i == 4)
- continue;
-
- assimilate = TRUE;
- rdst[c] = dst[c];
- dst[c] = alloc_temp(pc, NULL);
- }
}
switch (inst->Instruction.Opcode) {
@@ -1768,6 +1788,74 @@ prep_inspect_insn(struct nv50_pc *pc, const union tgsi_full_token *tok,
}
}
+/* Returns a bitmask indicating which dst components need to be
+ * written to temporaries first to avoid 'corrupting' sour...
2009 Jun 21
0
[PATCH] nv50: support for SLE, SNE, SEQ, SGT
...src1)
{
struct nv50_program_exec *e = exec(pc);
- unsigned inv_cop[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
struct nv50_reg *rdst;
- assert(c_op <= 7);
if (check_swap_src_0_1(pc, &src0, &src1))
- c_op = inv_cop[c_op];
+ c_op += 8;
rdst = dst;
- if (dst->type != P_TEMP)
- dst = alloc_temp(pc, NULL);
+ if (dst && dst->type != P_TEMP)
+ dst = temp_temp(pc);
/* set.u32 */
set_long(pc, e);
e->inst[0] |= 0xb0000000;
- e->inst[1] |= (3 << 29);
- e->inst[1] |= (c_op << 14);
- /*XXX: breaks things, .u32 by default?
- * decuda will disasm as .u16...
2009 Jun 21
0
[PATCH] nv50: initial support for IF, ELSE, ENDIF insns
...uct nv50_program_exec *if_insn[MAX_IF_LEVEL];
+ struct nv50_program_exec *if_join[MAX_IF_LEVEL];
+ unsigned if_lvl;
+
/* current instruction and total number of insns */
unsigned insn_cur;
unsigned insn_nr;
boolean allow32;
+ boolean join_on;
};
static inline void
@@ -208,22 +216,6 @@ alloc_temp(struct nv50_pc *pc, struct nv50_reg *dst)
return NULL;
}
-/* Assign the hw of the discarded temporary register src
- * to the tgsi register dst and free src.
- */
-static void
-assimilate_temp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
-{
- assert(src->index == -1 &...