Displaying 6 results from an estimated 6 matches for "align0".
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2012 Nov 09
0
[LLVMdev] [NVPTX] llc -march=nvptx64 -mcpu=sm_20 generates invalid zero align for device function params
...->getAlignment() == 0)
O << " .align " << (int) TD->getPrefTypeAlignment(ETy);
else
O << " .align " << GVar->getAlignment();
Could you please review and commit? Do you think it needs a test case?
Thanks,
- D.
dmikushin at hp2:~/forge/align0> llc -march=nvptx64 -mcpu=sm_20 align0.ll -o -
//
// Generated by LLVM NVPTX Back-End
//
.version 3.1
.target sm_20
.address_size 64
// .globl __internal_dsmul
.visible .func __internal_dsmul(
.param .b64 __internal_dsmul_param_0,
.param .align 4 .b8 __internal_dsmul_param_1[8],
.param .a...
2012 Jul 11
2
[LLVMdev] [NVPTX] llc -march=nvptx64 -mcpu=sm_20 generates invalid zero align for device function params
Hello,
FYI, this is a bug http://llvm.org/bugs/show_bug.cgi?id=13324
When compiling the following code for sm_20, func params are by some reason
given with .align 0, which is invalid. Problem does not occur if compiled
for sm_10.
> cat test.ll
; ModuleID = '__kernelgen_main_module'
target datalayout = "e-p:64:64-i64:64:64-f64:64:64-n1:8:16:32:64"
target triple =
2018 Jan 18
1
LEAQ instruction path
Hi,
I've been trying to teach LLVM that pointers are 128-bit long, which
segfaults with some seemingly unrelated stacktrace when I try to take an
address of a variable. Since stack saving and loading seems to work fine, I
dare to assume the instruction causing problems there is leaq. Now I've
done a search for leaq of the entire LLVM codebase with no success and I'd
like to know which
2012 Nov 09
0
[LLVMdev] [NVPTX] llc -march=nvptx64 -mcpu=sm_20 generates invalid zero align for device function params
Test cases exist under test/CodeGen/NVPTX (name changed in May). Now that
I'm back at NVIDIA, I'm going to be running through the bugzilla issues
(thanks Dmitry for the reports!). I have practically the exact same patch
here in my queue. :)
In this case, I would prefer ABI alignment for compatibility with the
vendor compiler. It should work either way, but I do need to audit the
2012 Nov 09
3
[LLVMdev] [NVPTX] llc -march=nvptx64 -mcpu=sm_20 generates invalid zero align for device function params
Hi Dmitry,
> You're right, global variables use preferred alignment. And - yes,
> preferred alignment in this case is bigger: 8 instead of 4. NVIDIA's
> prop. compiler gives 4. However, since CUDA 5.0 ptx modules are
> linkable with each other, I think alignments for externally visible
> functions and data should all follow ABI rules.
giving it an alignment of 8 does
2012 Sep 06
8
[LLVMdev] PROPOSAL: IR representation of detailed struct assignment information (new version)
Hello,
Persuant to feedback,
http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-August/052927.html
here is a new proposal for detailed struct assignment information.
Here's the example showing the basic problem:
struct bar {
char x;
float y;
double z;
};
void copy_bar(struct bar *a, struct bar *b) {
*a = *b;
}
The solution I now propose here is to have front-ends describe the copy
using