search for: alexsusu

...ts Verilog source code could be made open-source. You can find the source code of the latest version of the compiler (LLVM back end and extensions for Connex in the LoopVectorize module, etc) and runtime I develop for the Connex SIMD processor at this address: https://sites.google.com/site/alexsusu/myfilecabinet/OpincaaLLVM_REPO.zip . I would like to commit the Connex back end in the very near future in the LLVM repository. Also, the Opincaa runtime assembler library contains a great Connex SIMD processor simulator, which can be used in case you don't have access to the real proce...

Hello. I started implementing a back end in LLVM (and I'm writing some hints I consider useful at https://sites.google.com/site/alexsusu/home/backend-llvm ). Unfortunately, I hit quite a few times very cryptic error messages when compiling with TableGen, which required a few good hours of debugging the TableGen program. The most cryptic error message was when compiling with TableGen, with the option -gen-asm-matcher . H...