Displaying 3 results from an estimated 3 matches for "alexbradley".
2016 Oct 17
2
Generate Register Indirect mode instruction
...> %v3 = add i32 %v1, %v2
> store i32 %v3, i32* %c
>
> maps to (using invented mnemonics):
>
> ASSIGN R0, %a
> ASSIGN R1, %b
> ASSIGN R2, %c
> ADD *R2, *R0, *R1
>
> Thanks.
>
> Regards,
> Alex
>
> On 14 Oct 2016 1:00 p.m., "Alex Bradley" <alexbradley.bqc at gmail.com>
> wrote:
>
>>
>> > If I understand correctly:
>> >
>> > %v1 = load i32, i32* %a
>> > %v2 = load i32, i32* %b
>> > %v3 = add i32 %v1, %v2
>> > store i32 %v3, i32* %c
>> >
>> > maps to (using inve...
2016 Oct 14
2
Generate Register Indirect mode instruction
> If I understand correctly:
>
> %v1 = load i32, i32* %a
> %v2 = load i32, i32* %b
> %v3 = add i32 %v1, %v2
> store i32 %v3, i32* %c
>
> maps to (using invented mnemonics):
>
> ASSIGN R0, %a
> ASSIGN R1, %b
> ASSIGN R2, %c
> ADD *R2, *R0, *R1
>
> I.e. pattern
> (store %c, (add (load %a), (load %b)))
> becomes
> (ADD (ASSIGN R2, %c), (ASSIGN
2016 Oct 10
8
Generate Register Indirect mode instruction
Hi All,
I am new to llvm backend. I am trying out few examples to understand
backend codegen. I have ported llvm LEG @
https://github.com/frasercrmck/llvm-leg to llvm 3.9 successfully.
Currently, the LEG instructions are RISC load-store type instruction. I
want to generate some instructions for register indirect mode, like
following:
IR:
@a = local_unnamed_addr global i32 0, align 4
@b =