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Hey Everyone, I understood this a little differently (well, I do have direct contact with Sumeeth given that we both work in the same lab). Allow me to try and explain his proposal. We are trying to optimise out instructions from a program (JIT-compiled OS Kernels or JIT-compiled Web Server code) during run time and we have this hypothesis that some of the decisions are best taken by the

> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Kaylor, Andrew > Subject: Re: [LLVMdev] [Proposal] Adding callback mechanism to Execution Engines > If the function is in a statically linked module, you need to do something to explicitly expose it. With > the older JIT engine you can use addGlobalMapping as Yaron suggests, but I

Hey guys, I'm trying to implement a simplified X86_64 architecture targeting backend for LLVM. While I have figured that I can introduce the intended architecture as a subtarget of X86 in X86.td, what i don't understand is how the registers specified in X86RegisterInfo.td and the ISA in X86InstrInfo.td are correlated with each sub-architecture. Where are the correlations defined? The

Hey all, I am trying to implement a subtarget for the X86 architecture that only has 64 bit Registers. While running LLC on the IR for a very simple program, llc fails on an assertion that says it doesn't know how to promote ISD::FRAMEINDEX. I've tried to look for why how to promote the frameindex which is stored in a i32 variable to an i64 variable but can't seem to find where

Hey all, I am trying to implement a new subtarget for the X86 target that has only 64 bit registers and instructions and a very minimal ISA excluding any FPU instructions etc. I have made the required changes to the instructions such that all the instructions that I don't wish to use have a required<> clause that precludes them from being utilised when compiling for this subtarget.