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åkerlund
2020 Jun 08
2
Nested instruction patterns rejected by GlobalISel when having registers in Defs
...tterns.
Best regards,
Gabriel
_____
From: Daniel Sanders <daniel_l_sanders at apple.com>
Sent: Friday, June 5, 2020 9:02 PM
To: Quentin Colombet <qcolombet at apple.com>
Cc: Dominik Montada <dominik.montada at hightec-rt.com>; Gabriel Hjort Åkerlund
<gabriel.hjort.akerlund at ericsson.com>; llvm-dev at lists.llvm.org
<llvm-dev at lists.llvm.org>
Subject: Re: [llvm-dev] Nested instruction patterns rejected by GlobalISel
when having registers in Defs
The implicit defs don't participate much in the patterns. For the most part
it's just read into Co...
2020 Jun 04
2
Nested instruction patterns rejected by GlobalISel when having registers in Defs
...ted to modify that part of the
code, but maybe Im missing some invariant thats not immediately evident
Cheers,
Gabriel
From: Dominik Montada <dominik.montada at hightec-rt.com>
Sent: den 4 juni 2020 14:51
To: llvm-dev at lists.llvm.org
Cc: Gabriel Hjort Åkerlund <gabriel.hjort.akerlund at ericsson.com>
Subject: Re: [llvm-dev] Nested instruction patterns rejected by GlobalISel
when having registers in Defs
Hi Gabriel,
I'm working on a downstream target which uses GlobalISel and we have many
patterns with instructions that also define a system register as a
side-effect...
2020 Jun 04
2
Nested instruction patterns rejected by GlobalISel when having registers in Defs
Hi,
I am in the process of porting our target to GlobalISel, and have encountered a problem. Nearly all instructions in our instruction set make modifications to a CC register, and hence are defined as follows:
let ..., Defs = [CCReg] in
def shfts_a32_imm7: Instruction<(outs OurRC:$dst), ...>;
What's more, many of these instructions have patterns where the instruction itself