search for: aiml

...PCIe bridges cause devices to disappear from the PCIe bus after + * those were put into D3cold state if they were put into a non D0 PCI PM + * device state before doing so. + * + * This leads to various issue different issues which all manifest differently, + * but have the same root cause: + * - AIML code execution hits an infinite loop (as the coe waits on device + * memory to change). + * - kernel crashes, as all pci reads return -1, which most code isn't able + * to handle well enough. + * - sudden shutdowns, as the kernel identified an unrecoverable error after + * userspace...

...to D3cold, the device never comes back to D0. Right? > + * This leads to various issue different issues which all manifest differently, s/issue different// Actually, I think there's only one underlying issue with several manifestations. > + * but have the same root cause: > + * - AIML code execution hits an infinite loop (as the coe waits on device > + * memory to change). s/AIML/AML/ s/coe/code/ > + * - kernel crashes, as all pci reads return -1, which most code isn't able > + * to handle well enough. s/pci/PCI/ More details about these crashes would be...

...PCIe bridges cause devices to disappear from the PCIe bus after + * those were put into D3cold state if they were put into a non D0 PCI PM + * device state before doing so. + * + * This leads to various issue different issues which all manifest differently, + * but have the same root cause: + * - AIML code execution hits an infinite loop (as the coe waits on device + * memory to change). + * - kernel crashes, as all pci reads return -1, which most code isn't able + * to handle well enough. + * - sudden shutdowns, as the kernel identified an unrecoverable error after + * userspace...

...fter > > + * those were put into D3cold state if they were put into a non D0 PCI PM > > + * device state before doing so. > > + * > > + * This leads to various issue different issues which all manifest differently, > > + * but have the same root cause: > > + * - AIML code execution hits an infinite loop (as the coe waits on device > > + * memory to change). > > + * - kernel crashes, as all pci reads return -1, which most code isn't able > > + * to handle well enough. > > + * - sudden shutdowns, as the kernel identified an unr...

..., it fails. > > + * This leads to various issue different issues which all manifest differently, > > s/issue different// > > Actually, I think there's only one underlying issue with several > manifestations. > > > + * but have the same root cause: > > + * - AIML code execution hits an infinite loop (as the coe waits on device > > + * memory to change). > > s/AIML/AML/ > s/coe/code/ > > > + * - kernel crashes, as all pci reads return -1, which most code isn't able > > + * to handle well enough. > > s/pci/PCI/ &...

..._lenovo_thinkpad_p50_nvgpu); + +/* + * Some Intel PCIe bridge controllers cause devices to not reappear doing a + * D0 -> D3hot -> D3cold -> D0 sequence. Skipping the intermediate D3hot step + * seems to make it work again. + * + * This leads to various manifestations of this issue: + * - AIML code execution hits an infinite loop (as the coe waits on device + * memory to change). + * - kernel crashes, as all PCI reads return -1, which most code isn't able + * to handle well enough. + * - sudden shutdowns, as the kernel identified an unrecoverable error after + * userspace...

...disappear from the PCIe bus after > + * those were put into D3cold state if they were put into a non D0 PCI PM > + * device state before doing so. > + * > + * This leads to various issue different issues which all manifest differently, > + * but have the same root cause: > + * - AIML code execution hits an infinite loop (as the coe waits on device > + * memory to change). > + * - kernel crashes, as all pci reads return -1, which most code isn't able > + * to handle well enough. > + * - sudden shutdowns, as the kernel identified an unrecoverable error aft...

...PCIe bridges cause devices to disappear from the PCIe bus after + * those were put into D3cold state if they were put into a non D0 PCI PM + * device state before doing so. + * + * This leads to various issue different issues which all manifest differently, + * but have the same root cause: + * - AIML code execution hits an infinite loop (as the coe waits on device + * memory to change). + * - kernel crashes, as all pci reads return -1, which most code isn't able + * to handle well enough. + * - sudden shutdowns, as the kernel identified an unrecoverable error after + * userspace...

...various issue different issues which all manifest differently, > > > > s/issue different// > > > > Actually, I think there's only one underlying issue with several > > manifestations. > > > > > + * but have the same root cause: > > > + * - AIML code execution hits an infinite loop (as the coe waits on device > > > + * memory to change). > > > > s/AIML/AML/ > > s/coe/code/ > > > > > + * - kernel crashes, as all pci reads return -1, which most code isn't able > > > + * to handle...

...were put into D3cold state if they were put into a non D0 PCI PM > > > + * device state before doing so. > > > + * > > > + * This leads to various issue different issues which all manifest differently, > > > + * but have the same root cause: > > > + * - AIML code execution hits an infinite loop (as the coe waits on device > > > + * memory to change). > > > + * - kernel crashes, as all pci reads return -1, which most code isn't able > > > + * to handle well enough. > > > + * - sudden shutdowns, as the kern...

...e if they were put into a non D0 PCI PM > > > > + * device state before doing so. > > > > + * > > > > + * This leads to various issue different issues which all manifest differently, > > > > + * but have the same root cause: > > > > + * - AIML code execution hits an infinite loop (as the coe waits on device > > > > + * memory to change). > > > > + * - kernel crashes, as all pci reads return -1, which most code isn't able > > > > + * to handle well enough. > > > > + * - sudden sh...