Displaying 3 results from an estimated 3 matches for "afpr".
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afp
2012 Jan 31
4
[LLVMdev] (MC) Register parsing for AsmParser (standalone assembler)
...nt precision. All of which share the same register name.
/// Mips Single point precision FPU Registers
def F0 : FPR< 0, "F0">, DwarfRegNum<[32]>;
/// Mips Double point precision FPU Registers (aliased
/// with the single precision to hold 64 bit values)
def D0 : AFPR< 0, "F0", [F0, F1]>;
/// Mips Double point precision FPU Registers in MFP64 mode.
def D0_64 : AFPR64<0, "F0", [F0]>;
Notice that we currently need the symbolic name to be different (F0/D0/D0_64) for use in the codegen.
The examples here are from lib/Target...
2012 Feb 02
0
[LLVMdev] (MC) Register parsing for AsmParser (standalone assembler)
...e same register name.
>
> /// Mips Single point precision FPU Registers
> def F0 : FPR< 0, "F0">, DwarfRegNum<[32]>;
>
> /// Mips Double point precision FPU Registers (aliased
> /// with the single precision to hold 64 bit values)
> def D0 : AFPR< 0, "F0", [F0, F1]>;
>
> /// Mips Double point precision FPU Registers in MFP64 mode.
> def D0_64 : AFPR64<0, "F0", [F0]>;
>
> Notice that we currently need the symbolic name to be different (F0/D0/D0_64) for use in the codegen.
>
> Th...
2012 Feb 03
0
[LLVMdev] (MC) Register parsing for AsmParser (standalone assembler)
...e same register name.
>
> /// Mips Single point precision FPU Registers
> def F0 : FPR< 0, "F0">, DwarfRegNum<[32]>;
>
> /// Mips Double point precision FPU Registers (aliased
> /// with the single precision to hold 64 bit values)
> def D0 : AFPR< 0, "F0", [F0, F1]>;
>
> /// Mips Double point precision FPU Registers in MFP64 mode.
> def D0_64 : AFPR64<0, "F0", [F0]>;
>
> Notice that we currently need the symbolic name to be different (F0/D0/D0_64) for use in the codegen.
>
> Th...