Displaying 3 results from an estimated 3 matches for "aform_2".
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dform_2
2013 Mar 25
1
[LLVMdev] Types in TableGen instruction selection patterns
...write this:
>
> def insn : Inst<(outs i32:$dst), (ins i32:$src1, i32:$src2),
> "some assembler",
> [(set $dst, (Op $src1, $src2))]>;
>From the PPC changes, I see that this is already possible under a slightly
different form:
def FSUBS : AForm_2<59, 20,
(outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
"fsubs $FRT, $FRA, $FRB", FPGeneral,
- [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
+ [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;...
2013 Mar 25
0
[LLVMdev] Types in TableGen instruction selection patterns
Jakob Stoklund Olesen wrote:
> I have updated TableGen to support a new format for instruction selection patterns.
>
> Before:
>
> def : Pat<(subc IntRegs:$b, IntRegs:$c), (SUBCCrr IntRegs:$b, IntRegs:$c)>;
>
> After:
>
> def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>;
>
> Since the pattern matching happens on a DAG with type labels, not
2013 Mar 24
5
[LLVMdev] Types in TableGen instruction selection patterns
I have updated TableGen to support a new format for instruction selection patterns.
Before:
def : Pat<(subc IntRegs:$b, IntRegs:$c), (SUBCCrr IntRegs:$b, IntRegs:$c)>;
After:
def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>;
Since the pattern matching happens on a DAG with type labels, not register classes, I think it makes more sense to specify types directly on the input