search for: afgr64

...more sense now and it's looking like this issue isn't Mips specific. Here's the IR dump before simple register coalescing (note: I've patched the IR printer to print the contents of the regmask): 4480B %vreg260<def> = LDC1 %vreg253, <cp#3>[TF=6]; mem:LD8[ConstantPool] AFGR64:%vreg260 GPR32:%vreg253 4496B %vreg261<def> = FMUL_D32 %vreg247, %vreg248; AFGR64:%vreg261,%vreg247,%vreg248 4512B ADJCALLSTACKDOWN 16, %SP<imp-def>, %SP<imp-use> 4528B %D6<def> = COPY %vreg243; AFGR64:%vreg243 4544B JAL <ga:@sin>, <regmask %FP %RA %D10 %D11 %D1...

To reduce memory consumption clobbered registers are handled with RegisterMask machine operands which contain a bitset of all registers clobbered. - Matthias > On Jul 29, 2015, at 3:00 PM, Daniel Sanders <daniel.sanders at imgtec.com> wrote: > > I believe I've identified the problem with almabench but I haven't found the root cause in the compiler yet. > > The

...%vreg2 BB#0: derived from LLVM BB %entry SW %vreg2, <fi#-1>, 4; mem:ST4[FixedStack-1+4] CPURegs:%vreg2 SW %vreg1, <fi#-1>, 0; mem:ST4[FixedStack-1](align=8) CPURegs:%vreg1 %vreg3<def> = COPY %vreg0; CPURegs:%vreg3,%vreg0 %vreg4<def> = LDC1 <fi#-1>, 0; mem:LD8[%x2] AFGR64:%vreg4 The first two stores write the values in argument registers $6 and $7 to frame object -1 (Mips stores byval arguments passed in registers to the stack). The fourth instruction LDC1 loads the value written by the first two stores as a floating point double. This is the machine function jus...

...uot;l.d", FGR64, FGR64>; } // Instructions that convert an FP value to 32-bit fixed point. multiclass FFR1_W_M<bits<6> funct, string opstr> { def _S : FFR1<funct, 16, opstr, "w.s", FGR32, FGR32>; def _D32 : FFR1<funct, 17, opstr, "w.d", FGR32, AFGR64>, Requires<[NotFP64bit]>; def _D64 : FFR1<funct, 17, opstr, "w.d", FGR32, FGR64>, Requires<[IsFP64bit]> { let DecoderNamespace = "Mips64"; } } defm CEIL_W : FFR1_W_M<0xe, "ceil">; defm CEIL_L : FFR1_L_M&lt...

Hello, About a month ago, I submitted a set of patches for review on llvm-commit. The most controversial of the patches, http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20150622/d104ea7 1/attachment-0009.obj deals with the fact that before ARMv8, the rGPR RegClass in Thumb encodings didn't include SP; but from ARMv8 onwards, it does include it. RegClass membership is

...d from LLVM BB %entry > SW %vreg2, <fi#-1>, 4; mem:ST4[FixedStack-1+4] CPURegs:%vreg2 > SW %vreg1, <fi#-1>, 0; mem:ST4[FixedStack-1](align=8) CPURegs:%vreg1 > %vreg3<def> = COPY %vreg0; CPURegs:%vreg3,%vreg0 > %vreg4<def> = LDC1 <fi#-1>, 0; mem:LD8[%x2] AFGR64:%vreg4 > > > The first two stores write the values in argument registers $6 and $7 > to frame object -1 > (Mips stores byval arguments passed in registers to the stack). > The fourth instruction LDC1 loads the value written by the first two > stores as a floating point double...

...;; > } > > // Instructions that convert an FP value to 32-bit fixed point. > multiclass FFR1_W_M<bits<6> funct, string opstr> { > def _S : FFR1<funct, 16, opstr, "w.s", FGR32, FGR32>; > def _D32 : FFR1<funct, 17, opstr, "w.d", FGR32, AFGR64>, > Requires<[NotFP64bit]>; > def _D64 : FFR1<funct, 17, opstr, "w.d", FGR32, FGR64>, > Requires<[IsFP64bit]> { > let DecoderNamespace = "Mips64"; > } > } > > defm CEIL_W : FFR1_W_M<0xe, "ce...

...SW %vreg2, <fi#-1>, 4; mem:ST4[FixedStack-1+4] CPURegs:%vreg2 >>       SW %vreg1, <fi#-1>, 0; mem:ST4[FixedStack-1](align=8) CPURegs:%vreg1 >>       %vreg3<def> = COPY %vreg0; CPURegs:%vreg3,%vreg0 >>       %vreg4<def> = LDC1 <fi#-1>, 0; mem:LD8[%x2] AFGR64:%vreg4 >> >> >> The first two stores write the values in argument registers $6 and $7 >> to frame object -1 >> (Mips stores byval arguments passed in registers to the stack). >> The fourth instruction LDC1 loads the value written by the first two >> stores...

Hello, why LLVM does not define physical register limits for MIPS by overriding the TargetRegisterInfo::getRegPressureLimit function the way it’s done for X86 in x86RegisterInfo.cpp and ARM. Thanks in advance. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120818/a8e4f353/attachment.html>

...<fi#-1>, 4; mem:ST4[FixedStack-1+4] CPURegs:%vreg2 >>> SW %vreg1, <fi#-1>, 0; mem:ST4[FixedStack-1](align=8) CPURegs:%vreg1 >>> %vreg3<def> = COPY %vreg0; CPURegs:%vreg3,%vreg0 >>> %vreg4<def> = LDC1 <fi#-1>, 0; mem:LD8[%x2] AFGR64:%vreg4 >>> >>> >>> The first two stores write the values in argument registers $6 and $7 >>> to frame object -1 >>> (Mips stores byval arguments passed in registers to the stack). >>> The fourth instruction LDC1 loads the value written by the...

...;, 4; mem:ST4[FixedStack-1+4] CPURegs:%vreg2 >>>>       SW %vreg1, <fi#-1>, 0; mem:ST4[FixedStack-1](align=8) CPURegs:%vreg1 >>>>       %vreg3<def> = COPY %vreg0; CPURegs:%vreg3,%vreg0 >>>>       %vreg4<def> = LDC1 <fi#-1>, 0; mem:LD8[%x2] AFGR64:%vreg4 >>>> >>>> >>>> The first two stores write the values in argument registers $6 and $7 >>>> to frame object -1 >>>> (Mips stores byval arguments passed in registers to the stack). >>>> The fourth instruction LDC1 loads the...

Hi, Mips32 has 64 bit floating point instructions, while i64 instructions have to be emulated with i32 instructions. This means that G_LOAD should be custom legalized for s64 integer value, and be legal for s64 floating point value. There are also other generic instructions with the same problem: G_STORE, G_SELECT, G_EXTRACT, and G_INSERT. There are also other configurations where integer