search for: aesni

...; +static struct crypto_alg virtio_crypto_algs[] = { { >>> + .cra_name = "cbc(aes)", >>> + .cra_driver_name = "virtio_crypto_aes_cbc", >>> + .cra_priority = 501, >> >> >> This is still higher than the hardware-accelerators (like intel aesni or the >> s390 cpacf functions or the arm hw). aesni and s390/cpacf are supported by the >> hardware virtualization and available to the guests. I do not see a way how >> virtio >> crypto can be faster than that (in the end it might be cpacf/aesni + overhead) >> instea...

...; +static struct crypto_alg virtio_crypto_algs[] = { { >>> + .cra_name = "cbc(aes)", >>> + .cra_driver_name = "virtio_crypto_aes_cbc", >>> + .cra_priority = 501, >> >> >> This is still higher than the hardware-accelerators (like intel aesni or the >> s390 cpacf functions or the arm hw). aesni and s390/cpacf are supported by the >> hardware virtualization and available to the guests. I do not see a way how >> virtio >> crypto can be faster than that (in the end it might be cpacf/aesni + overhead) >> instea...

...> >>>> + .cra_name = "cbc(aes)", > >>>> + .cra_driver_name = "virtio_crypto_aes_cbc", > >>>> + .cra_priority = 501, > >>> > >>> > >>> This is still higher than the hardware-accelerators (like intel aesni or the > >>> s390 cpacf functions or the arm hw). aesni and s390/cpacf are supported by the > >>> hardware virtualization and available to the guests. I do not see a way how > >>> virtio > >>> crypto can be faster than that (in the end it might be cpa...

...> >>>> + .cra_name = "cbc(aes)", > >>>> + .cra_driver_name = "virtio_crypto_aes_cbc", > >>>> + .cra_priority = 501, > >>> > >>> > >>> This is still higher than the hardware-accelerators (like intel aesni or the > >>> s390 cpacf functions or the arm hw). aesni and s390/cpacf are supported by the > >>> hardware virtualization and available to the guests. I do not see a way how > >>> virtio > >>> crypto can be faster than that (in the end it might be cpa...

...15/2016 03:03 AM, Gonglei wrote: [...] > + > +static struct crypto_alg virtio_crypto_algs[] = { { > + .cra_name = "cbc(aes)", > + .cra_driver_name = "virtio_crypto_aes_cbc", > + .cra_priority = 501, This is still higher than the hardware-accelerators (like intel aesni or the s390 cpacf functions or the arm hw). aesni and s390/cpacf are supported by the hardware virtualization and available to the guests. I do not see a way how virtio crypto can be faster than that (in the end it might be cpacf/aesni + overhead) instead it will very likely be slower. So we should...

...15/2016 03:03 AM, Gonglei wrote: [...] > + > +static struct crypto_alg virtio_crypto_algs[] = { { > + .cra_name = "cbc(aes)", > + .cra_driver_name = "virtio_crypto_aes_cbc", > + .cra_priority = 501, This is still higher than the hardware-accelerators (like intel aesni or the s390 cpacf functions or the arm hw). aesni and s390/cpacf are supported by the hardware virtualization and available to the guests. I do not see a way how virtio crypto can be faster than that (in the end it might be cpacf/aesni + overhead) instead it will very likely be slower. So we should...

...l as Position Independent Executable (PIE) on x86_64. Another patchset will add the PIE option and larger architecture changes. The patches: - 1, 3-11: Change in assembly code to be PIE compliant. - 2: Add a new _ASM_MOVABS macro to fetch a symbol address generically. diffstat: crypto/aegis128-aesni-asm.S | 6 +- crypto/aegis128l-aesni-asm.S | 8 +-- crypto/aegis256-aesni-asm.S | 6 +- crypto/aes-x86_64-asm_64.S | 45 ++++++++++------ crypto/aesni-intel_asm.S | 8 +-- crypto/aesni-intel_avx-x86_64.S | 3 - crypto/camellia-aesni-av...

...l as Position Independent Executable (PIE) on x86_64. Another patchset will add the PIE option and larger architecture changes. The patches: - 1, 3-11: Change in assembly code to be PIE compliant. - 2: Add a new _ASM_MOVABS macro to fetch a symbol address generically. diffstat: crypto/aegis128-aesni-asm.S | 6 +- crypto/aegis128l-aesni-asm.S | 8 +-- crypto/aegis256-aesni-asm.S | 6 +- crypto/aes-x86_64-asm_64.S | 45 ++++++++++------ crypto/aesni-intel_asm.S | 8 +-- crypto/aesni-intel_avx-x86_64.S | 3 - crypto/camellia-aesni-av...

...alg virtio_crypto_algs[] = { { >>>> + .cra_name = "cbc(aes)", >>>> + .cra_driver_name = "virtio_crypto_aes_cbc", >>>> + .cra_priority = 501, >>> >>> >>> This is still higher than the hardware-accelerators (like intel aesni or the >>> s390 cpacf functions or the arm hw). aesni and s390/cpacf are supported by the >>> hardware virtualization and available to the guests. I do not see a way how >>> virtio >>> crypto can be faster than that (in the end it might be cpacf/aesni + overhead)...

...E) on x86_64. Another patchset will > add the PIE option and larger architecture changes. > > The patches: > - 1, 3-11: Change in assembly code to be PIE compliant. > - 2: Add a new _ASM_MOVABS macro to fetch a symbol address generically. > > diffstat: > crypto/aegis128-aesni-asm.S | 6 +- > crypto/aegis128l-aesni-asm.S | 8 +-- > crypto/aegis256-aesni-asm.S | 6 +- > crypto/aes-x86_64-asm_64.S | 45 ++++++++++------ > crypto/aesni-intel_asm.S | 8 +-- > crypto/aesni-intel_avx-x86_64.S | 3 -...

...l to be PIE compatible. Position Independent Executable (PIE) support will allow to extended the KASLR randomization range below the -2G memory limit. Signed-off-by: Thomas Garnier <thgarnie at google.com> --- arch/x86/crypto/aes-x86_64-asm_64.S | 45 ++++++++----- arch/x86/crypto/aesni-intel_asm.S | 14 ++-- arch/x86/crypto/aesni-intel_avx-x86_64.S | 6 +- arch/x86/crypto/camellia-aesni-avx-asm_64.S | 42 ++++++------ arch/x86/crypto/camellia-aesni-avx2-asm_64.S | 44 ++++++------- arch/x86/crypto/camellia-x86_64-asm_64.S | 8 ++- arch/x86/crypto/cast5-avx-x...

...as Position Independent Executable (PIE) on x86_64. Another patchset will add the PIE option and larger architecture changes. The patches: - 1-2, 4-12: Change in assembly code to be PIE compliant. - 3: Add a new _ASM_MOVABS macro to fetch a symbol address generically. diffstat: crypto/aegis128-aesni-asm.S | 6 +- crypto/aegis128l-aesni-asm.S | 8 +-- crypto/aegis256-aesni-asm.S | 6 +- crypto/aes-x86_64-asm_64.S | 45 ++++++++++------ crypto/aesni-intel_asm.S | 8 +-- crypto/camellia-aesni-avx-asm_64.S | 42 +++++++-------- crypto/cam...

...gt; > + > > +static struct crypto_alg virtio_crypto_algs[] = { { > > + .cra_name = "cbc(aes)", > > + .cra_driver_name = "virtio_crypto_aes_cbc", > > + .cra_priority = 501, > > > This is still higher than the hardware-accelerators (like intel aesni or the > s390 cpacf functions or the arm hw). aesni and s390/cpacf are supported by the > hardware virtualization and available to the guests. I do not see a way how > virtio > crypto can be faster than that (in the end it might be cpacf/aesni + overhead) > instead it will very likel...

...config | 45 ++++++ arch/x86/Makefile | 58 ++++++++ arch/x86/boot/boot.h | 2 arch/x86/boot/compressed/Makefile | 5 arch/x86/boot/compressed/misc.c | 10 + arch/x86/crypto/aegis128-aesni-asm.S | 6 arch/x86/crypto/aegis128l-aesni-asm.S | 8 - arch/x86/crypto/aegis256-aesni-asm.S | 6 arch/x86/crypto/aes-x86_64-asm_64.S | 45 ++++-- arch/x86/crypto/aesni-intel_asm.S | 8 - arch/x86/crypto/aesni-intel_avx-x86_64.S | 6...

...devices/platform/pcspkr/input/input4 [ 3.351981] piix4_smbus 0000:00:01.3: SMBus base address uninitialized - upgrade BIOS or use force_addr=0xaddr [ 3.502014] ppdev: user-space parallel port driver [ 3.539306] AES CTR mode by8 optimization enabled [ 3.590103] alg: No test for __gcm-aes-aesni (__driver-gcm-aes-aesni) [ 3.635925] alg: No test for crc32 (crc32-pclmul) [ 3.659506] type=1305 audit(1433643281.958:4): audit_pid=472 old=0 auid=4294967295 ses=4294967295 subj=system_u:system_r:auditd_t:s0 res=1 [ 4.084861] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready [ 9.575888...

...s 10 # /usr/sfw/bin/openssl engine -c -t # cc -fast*-I /usr/sfw/include -L /usr/sfw/lib -lcrypto* aes_test.c -o aes_test.out http://blogs.oracle.com/DanX/entry/sparc_t4_openssl_engine http://blogs.oracle.com/DanX/entry/where_s_the_crypto_libraries http://blogs.oracle.com/DanX/entry/solaris_x86_aesni_openssl_engine http://blogs.oracle.com/chichang1/entry/rsa_performance_of_sun_fire Here is some info from my intel box Solaris 11 # /usr/bin/openssl engine -c -t (aesni) Intel AES-NI engine (no-aesni) % no-aesni means no aes H/W acceleration [ available ] (dynamic) Dynamic engine loading...

...40 +++++ >> arch/x86/boot/boot.h | 2 >> arch/x86/boot/compressed/Makefile | 5 >> arch/x86/boot/compressed/misc.c | 10 + >> arch/x86/crypto/aes-x86_64-asm_64.S | 45 ++++-- >> arch/x86/crypto/aesni-intel_asm.S | 14 +- >> arch/x86/crypto/aesni-intel_avx-x86_64.S | 6 >> arch/x86/crypto/camellia-aesni-avx-asm_64.S | 42 +++--- >> arch/x86/crypto/camellia-aesni-avx2-asm_64.S | 44 +++--- >> arch/x86/crypto/camellia-x86_64-asm_64.S | 8...

...40 +++++ >> arch/x86/boot/boot.h | 2 >> arch/x86/boot/compressed/Makefile | 5 >> arch/x86/boot/compressed/misc.c | 10 + >> arch/x86/crypto/aes-x86_64-asm_64.S | 45 ++++-- >> arch/x86/crypto/aesni-intel_asm.S | 14 +- >> arch/x86/crypto/aesni-intel_avx-x86_64.S | 6 >> arch/x86/crypto/camellia-aesni-avx-asm_64.S | 42 +++--- >> arch/x86/crypto/camellia-aesni-avx2-asm_64.S | 44 +++--- >> arch/x86/crypto/camellia-x86_64-asm_64.S | 8...

...and larger architecture changes. PIE allows the kernel to be placed below the 0xffffffff80000000 increasing the range of KASLR. The patches: - 1, 3-11: Change in assembly code to be PIE compliant. - 2: Add a new _ASM_MOVABS macro to fetch a symbol address generically. diffstat: crypto/aegis128-aesni-asm.S | 6 +- crypto/aesni-intel_asm.S | 8 +-- crypto/aesni-intel_avx-x86_64.S | 3 - crypto/camellia-aesni-avx-asm_64.S | 42 +++++++-------- crypto/camellia-aesni-avx2-asm_64.S | 44 ++++++++-------- crypto/camellia-x86_64-asm_64.S | 8 +-- crypto/cast...

...and larger architecture changes. PIE allows the kernel to be placed below the 0xffffffff80000000 increasing the range of KASLR. The patches: - 1, 3-11: Change in assembly code to be PIE compliant. - 2: Add a new _ASM_MOVABS macro to fetch a symbol address generically. diffstat: crypto/aegis128-aesni-asm.S | 6 +- crypto/aesni-intel_asm.S | 8 +-- crypto/aesni-intel_avx-x86_64.S | 3 - crypto/camellia-aesni-avx-asm_64.S | 42 +++++++-------- crypto/camellia-aesni-avx2-asm_64.S | 44 ++++++++-------- crypto/camellia-x86_64-asm_64.S | 8 +-- crypto/cast...