Displaying 2 results from an estimated 2 matches for "ae818d4e".
2008 Nov 11
0
[LLVMdev] Custom lowering binary operations on one register machines.
On Nov 10, 2008, at 9:51 AM, sanjiv gupta wrote:
> Ours is an accumulator based architecture.
>
> So one operand of ADD/SUB operations is in REG (accumulator) and the
> other one is in Memory. The result can be left either in REG or
> memory.
>
> The LLVM DAG for such operations expect both operands in REG.
>
> for example:
> char a, b, c, d, e;
> a = (b - c) +
2008 Nov 10
2
[LLVMdev] Custom lowering binary operations on one register machines.
Ours is an accumulator based architecture.
So one operand of ADD/SUB operations is in REG (accumulator) and the
other one is in Memory. The result can be left either in REG or memory.
The LLVM DAG for such operations expect both operands in REG.
for example:
char a, b, c, d, e;
a = (b - c) + (d - e);
generates
addc:i8 (subc:i8(b,c), subc:i8(d,e))
Looks like we need to custom lower addc