search for: adx

...EA4D8F8,0x3EAF8F6D,0x3EBAF81A, 0x3EC71E95,0x3ED40F33,0x3EE1D716, 0x3EF0843C,0x3F0012C6,0x3F086571, 0x3F114293,0x3F1AB32B,0x3F24C0CE, 0x3F2F75B1,0x3F3ADCB2,0x3F470165, 0x3F53F01D,0x3F61B5FB,0x3F7060FB, 0x3F800000 }; tatic void render_line(int x0,int x1,int y0,int y1,float *d){ int dy=y1-y0; int adx=x1-x0; int ady=abs(dy); int base=dy/adx; int sy=(dy<0?base-1:base+1); int x=x0; int y=y0; int err=0; ady-=abs(base*adx); d[x]*=*((float *)&FLOOR_fromdB_LOOKUP[y]); while(++x<x1){ err=err+ady; if(err>=adx){ err-=adx; y+=sy; }else{ y+=bas...

Hi I am trying to use tree() to classify movements in a futures contract. My data is like this: diff dip dim adx 1 0 100.00000 8650.0000 100.00000 2 0 93.18540 2044.5455 93.18540 3 0 90.30995 1549.1169 90.30995 4 1 85.22030 927.0419 85.22030 5 1 85.36084 785.6480 85.36084 6 0 85.72627 663.3814...

Hi, AFAIK there should be a single DNS SRV record for PDC role in the domain, e.g.: _ldap._tcp.pdc._msdcs.adx.mobiltel.bg. 900 IN SRV 0 100 389 dc01.example.com. When doing a 'samba-tool fsmo transfer --role=pdc' on dc02, the reole is being transferred and a new DNS record added, but the old one for dc01 is not removed. Is there anything not working correctly in my setup or does it need to be remo...

...fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch ida arat epb xsaveopt pln pts dtherm hwp hwp_noitfy hwp_act_window hwp_epp tpr_shadow vnmi flexpriority ept vpid fsgsbase bmi1 hle avx2 smep bmi2 erms invpcid rtm rdseed adx bogomips : 6816.05 clflush size : 64 cache_alignment : 64 address sizes : 39 bits physical, 48 bits virtual power management: Linux srv-s01.ccds.de 2.6.32-696.1.1.el6.x86_64 #1 SMP Tue Apr 11 17:13:24 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux -- LF

...;-as.xts(read.zoo("~/R/Data/EURUSD60.csv",sep=",",format="%Y-%m-%d %R",tz="GMT",header=T)) I then set up a couple of indicators and the following model: myATR <- function(x) ATR(HLC(x))[,'atr'] mySMI <- function(x) SMI(HLC(x))[,'SMI'] myADX <- function(x) ADX(HLC(x))[,'ADX'] myAroon <- function(x) aroon(x[,c('High','Low')])$oscillator myBB <- function(x) BBands(HLC(x))[,'pctB'] myChaikinVol<-function(x)Delt(chaikinVolatility(x[,c("High","Low")]))[,1] myCLV <- function(...

...cnt,+aes,+xsaves,-avx512er,-avx512vpopcntdq,-clwb,-avx512f,-clzero,-pku,+mmx,-lwp,-xop,+rdseed,-sse4a,-avx512bw,+clflushopt,+xsave,-avx512vl,-avx512cd,+avx,-rtm,+fma,+bmi,+rdrnd,-mwaitx,+sse4.1,+sse4.2,+avx2,+sse,+lzcnt,+pclmul,-prefetchwt1,+f16c,+ssse3,+sgx,+cmov,-avx512vbmi,+movbe,+xsaveopt,-sha,+adx,-avx512pf,+sse3 It successfully creates a binary, but the binary when run crashes with: Unhandled exception at 0x00007FF7C9913BA7 in test.exe: 0xC0000005: Access violation reading location 0xFFFFFFFFFFFFFFFF. The disassembly of the crashed instruction is: 00007FF7C9913BA7 vmovdqa xmmword...

...vector [floor1_final_Y] element [i] = [predicted] - (([val] - 1) divided by 2 using integer division) hould be: 21) vector [floor1_final_Y] element [i] = [predicted] - (([val] + 1) divided by 2 using integer division) <p>- in the function render_line 11) [ady] = [ady] - [base] * [adx] hould be: 11) [ady] = [ady] - absolute value of [base] * [adx] <p>Also, the parameter order of render_point(x0,x1,y0,y1,X) and render_line(x0, y0, x1, y1, v) is not consistent, and the references to the render_line function use different ordering: - Floor 1 / curve computation / step 2:...

..., otherwise the following may do the trick: move steps 25) .. 28) to the top, e.g. behind step 1) in step 5) (but not in step 6) replace the two occurrences of [floor1_Y] with [floor1_final_Y]. --- #3: in helper.html, function render_line: Replace 11) with 11) [ady] = [ady] - abs ( [base] ) * [adx] --- That's all I can think of at the moment. Any comments? Henning <p>--- >8 ---- List archives: http://www.xiph.org/archives/ Ogg project homepage: http://www.xiph.org/ogg/ To unsubscribe from this list, send a message to 'vorbis-dev-request@xiph.org' containing only the...

...on is what and what I can do about it? here is the flags part of lscpu in native and vm: https://dpaste.com/3TR8QJ5G8 and the vm's xml: https://dpaste.com/984JX4LUQ if I build the image with the default flags (march=x86-64), the vm boots well. my new chost is -O2 -pipe -march=skylake -mabm -mno-adx -mno-avx -mno-avx2 -mno-bmi -mno-bmi2 -mno-f16c -mno-fma -mno-xsave -mno-xsavec -mno-xsaveopt -mno-xsaves -mno-sgx the cpu is Intel(R) Pentium(R) CPU G4560 @ 3.50GHz thoughts? Thanks, Dagg.

...fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch ida arat epb xsaveopt pln pts dtherm hwp hwp_noitfy hwp_act_window hwp_epp tpr_shadow vnmi flexpriority ept vpid fsgsbase bmi1 hle avx2 smep bmi2 erms invpcid rtm rdseed adx > bogomips : 6816.05 > clflush size : 64 > cache_alignment : 64 > address sizes : 39 bits physical, 48 bits virtual > power management: > > Linux srv-s01.ccds.de 2.6.32-696.1.1.el6.x86_64 #1 SMP Tue Apr 11 17:13:24 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux > > -- > LF H...

...t; <feature name='smep'/> <feature name='bmi2'/> <feature name='erms'/> <feature name='invpcid'/> <feature name='rtm'/> <feature name='rdseed'/> <feature name='adx'/> <feature name='smap'/> <feature name='md-clear'/> <feature name='ssbd'/> <feature name='xsaveopt'/> <feature name='pdpe1gb'/> <feature name='rdtscp'/> <f...

Hi, For some maybe dumb reasons I try to write a portable version of int128. What is very valuable for this implementation is access to MUL instruction on x86 which provides full 64 x 64 -> 128 bit multiplication. An equally useful on ARM would be UMULH instruction. Well, the way you can access this on clang / GCC is to use __int128 type or use inline assembly. MSVC provides an intrinsic for

...er,-avx512vpopcntdq,-clwb,-avx512f,-clzero,-pku,+mmx,- > lwp,-xop,+rdseed,-sse4a,-avx512bw,+clflushopt,+xsave,- > avx512vl,-avx512cd,+avx,-rtm,+fma,+bmi,+rdrnd,-mwaitx,+sse4. > 1,+sse4.2,+avx2,+sse,+lzcnt,+pclmul,-prefetchwt1,+f16c,+ > ssse3,+sgx,+cmov,-avx512vbmi,+movbe,+xsaveopt,-sha,+adx,-avx512pf,+sse3 > > > It successfully creates a binary, but the binary when run crashes with: > > Unhandled exception at 0x00007FF7C9913BA7 in test.exe: 0xC0000005: Access > violation reading location 0xFFFFFFFFFFFFFFFF. > > The disassembly of the crashed instruction is: &gt...

...sult of an actual calculation was wrong. So, it's not only the text version of the assembler also the machine assembler is wrong. When I execute the exploit program on an Intel KNL the following output is produced: CPU name = knl -sse4a,-avx512bw,cx16,-tbm,xsave,-fma4,-avx512vl,prfchw,bmi2,adx,-xsavec,fsgsbase,avx,avx512cd,avx512pf,-rtm,popcnt,fma,bmi,aes,rdrnd,-xsaves,sse4.1,sse4.2,avx2,avx512er,sse,lzcnt,pclmul,avx512f,f16c,ssse3,mmx,-pku,cmov,-xop,rdseed,movbe,-hle,xsaveopt,-sha,sse2,sse3,-avx512dq, Assembly: .text .file "module_KFxOBX_i4_after.ll" .globl...

..."="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="knl" "target-features"="+adx,+aes,+avx,+avx2,+avx512cd,+avx512er,+avx512f,+avx512pf,+bmi,+bmi2,+cx16,+f16c,+fma,+fsgsbase,+fxsr,+lzcnt,+mmx,+movbe,+pclmul,+popcnt,+prefetchwt1,+rdrnd,+rdseed,+rtm,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt" "unsafe-fp-math"="false" "use-soft-floa...

...o, it's not only the text version of > the > assembler also the machine assembler is wrong. > > When I execute the exploit program on an Intel KNL the following > output > is produced: > > CPU name = knl > -sse4a,-avx512bw,cx16,-tbm,xsave,-fma4,-avx512vl,prfchw,bmi2,adx,-xsavec,fsgsbase,avx,avx512cd,avx512pf,-rtm,popcnt,fma,bmi,aes,rdrnd,-xsaves,sse4.1,sse4.2,avx2,avx512er,sse,lzcnt,pclmul,avx512f,f16c,ssse3,mmx,-pku,cmov,-xop,rdseed,movbe,-hle,xsaveopt,-sha,sse2,sse3,-avx512dq, > Assembly: > .text > .file "module_KFxOBX_i4_after.ll&quot...

..._2 x2apic movbe popcnt >> tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch ida >> arat epb xsaveopt pln pts dtherm hwp hwp_noitfy hwp_act_window hwp_epp >> tpr_shadow vnmi flexpriority ept vpid fsgsbase bmi1 hle avx2 smep bmi2 erms >> invpcid rtm rdseed adx >> bogomips : 6816.05 >> clflush size : 64 >> cache_alignment : 64 >> address sizes : 39 bits physical, 48 bits virtual >> power management: >> >> Linux srv-s01.ccds.de 2.6.32-696.1.1.el6.x86_64 #1 SMP Tue Apr 11 >> 17:13:24 UTC 2017 x86_6...

...ulx_u64 intrinsic, but it currently requires the hardware > flag "-mbmi2". > > https://github.com/Quuxplusone/WideIntProofOfConcept/blob/master/wider.h#L89-L99 > > On Clang 3.8.1 and earlier, the _addcarry_u64 and _subborrow_u64 > intrinsics required the hardware flag `-madx`, even though they didn't use > the hardware ADX/ADOX instructions. Modern GCC and Clang permit the use of > these intrinsics (to generate ADC) even in the absence of `-madx`. > > I think it would be a very good idea for Clang to support _mulx_u64 (to > generate MUL) even in the...

...ion of >> the >> assembler also the machine assembler is wrong. >> >> When I execute the exploit program on an Intel KNL the following >> output >> is produced: >> >> CPU name = knl >> -sse4a,-avx512bw,cx16,-tbm,xsave,-fma4,-avx512vl,prfchw,bmi2,adx,-xsavec,fsgsbase,avx,avx512cd,avx512pf,-rtm,popcnt,fma,bmi,aes,rdrnd,-xsaves,sse4.1,sse4.2,avx2,avx512er,sse,lzcnt,pclmul,avx512f,f16c,ssse3,mmx,-pku,cmov,-xop,rdseed,movbe,-hle,xsaveopt,-sha,sse2,sse3,-avx512dq, >> Assembly: >> .text >> .file "module_KFxOBX_i4...

...uot;no-nans-fp-math"="false" >> "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" >> "stack-protector-buffer-size"="8" "target-cpu"="knl" >> "target-features"="+adx,+aes,+avx,+avx2,+avx512cd,+avx512er, >> +avx512f,+avx512pf,+bmi,+bmi2,+cx16,+f16c,+fma,+fsgsbase,+fx >> sr,+lzcnt,+mmx,+movbe,+pclmul,+popcnt,+prefetchwt1,+rdrnd,+ >> rdseed,+rtm,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt" >> "unsafe-fp-math&quot...