Displaying 5 results from an estimated 5 matches for "addrsi".
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2012 Feb 20
1
[LLVMdev] ARM opcode format
I'm doing some tests running llvm on Android. I'm getting an error message
saying:
Unhandled instruction encoding format!
I checked which instruction was causing this and it is ADDrsi, it appears
to have format 42 << 7, which is definitely not available in ARMBaseInfo.h
Any suggestions are welcome
--
Guillermo A. Pérez (吉耶莫)
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2012 Feb 20
2
[LLVMdev] ARM opcode format
...] ARM opcode format****
>
> ** **
>
> I'm doing some tests running llvm on Android. I'm getting an error message
> saying:****
>
> ** **
>
> Unhandled instruction encoding format!****
>
> ** **
>
> I checked which instruction was causing this and it is ADDrsi, it appears
> to have format 42 << 7, which is definitely not available in ARMBaseInfo.h
> ****
>
> ** **
>
> Any suggestions are welcome
> ****
>
> ** **
>
> --
> Guillermo A. Pérez (吉耶莫)****
>
--
Guillermo A. Pérez (吉耶莫)
-------------- next part --...
2013 Apr 24
1
[LLVMdev] use of ARM GPRPair register class
...ctions to use a GPRPair sub-register.
The copy into %vreg4 asserts because of the two definitions of vreg9,
coming from vreg9:gsub_0 and vreg9:gsub_1.
%vreg1<def> = COPY %R1; GPR:%vreg1
%vreg2<def> = MOVi32imm <ga:@a>; GPR:%vreg2
%vreg3<def> = ADDrsi %vreg2<kill>, %vreg1, 18, pred:14, pred:%noreg,
opt:%noreg; GPR:%vreg3,%vreg2,%vreg1
%vreg9:gsub_0<def,read-undef> = LDRi12 %vreg3, 112, pred:14,
pred:%noreg; mem:LD4[%arrayidx83](tbaa=!"int") GPRPair:%vreg9 :%vreg3
%vreg9:gsub_1<def,read-undef> = LDRi1...
2012 Feb 20
0
[LLVMdev] ARM opcode format
...2012 07:48
To: llvmdev at cs.uiuc.edu<mailto:llvmdev at cs.uiuc.edu>
Subject: [LLVMdev] ARM opcode format
I'm doing some tests running llvm on Android. I'm getting an error message saying:
Unhandled instruction encoding format!
I checked which instruction was causing this and it is ADDrsi, it appears to have format 42 << 7, which is definitely not available in ARMBaseInfo.h
Any suggestions are welcome
--
Guillermo A. Pérez (吉耶莫)
--
Guillermo A. Pérez (吉耶莫)
-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If...
2012 Feb 20
3
[LLVMdev] ARM opcode format
...] ARM opcode format****
>
> ****
>
> I'm doing some tests running llvm on Android. I'm getting an error message
> saying:****
>
> ****
>
> Unhandled instruction encoding format!****
>
> ****
>
> I checked which instruction was causing this and it is ADDrsi, it appears
> to have format 42 << 7, which is definitely not available in ARMBaseInfo.h
> ****
>
> ****
>
> Any suggestions are welcome
> ****
>
> ****
>
> --
> Guillermo A. Pérez (吉耶莫)****
>
>
>
> ****
>
> ** **
>
> --
> Guill...