Displaying 3 results from an estimated 3 matches for "addrreg1".
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2014 Dec 14
2
[LLVMdev] ScheduleDAGInstrs.cpp
...oad i64* %_tmp256
which means the same address is loaded twice, first to store a value, and then to load it back.
The MachineInstructions to load an i64 are first pseudos and are then split post regalloc and become
SU(0): addrReg0 = load *fp(-50) // Two address registers with same value
SU(1): addrReg1 = load *fp(-50)
SU(2): store dataReg0:lo, *addrReg0(2) // Store a register in two parts
SU(3): store dataReg0:hi, *addrReg0
SU(4): dataReg1:lo = load *addrReg1(2) // Load a register in two parts
SU(5): dataReg1:hi = load *addrReg1
Since the addresses are loaded from memory, the underlying Objs bec...
2014 Dec 08
3
[LLVMdev] ScheduleDAGInstrs.cpp
Hi,
Can anyone help me to understand the ScheduleDAGInstrs::buildSchedGraph() method?
I find the handling of AliasChain is disturbing since:
1. A new alias chain add deps to all possibly aliasing SUs, and then clears those lists.
2. When AliasChain is present, the addChainDependency() method is called,
but the target hook areMemAccessesTriviallyDisjoint() called inside
2014 Dec 16
3
[LLVMdev] ScheduleDAGInstrs.cpp
...the same address is loaded twice, first to store a value, and then to load it back.
>
> The MachineInstructions to load an i64 are first pseudos and are then
> split post regalloc and become
>
> SU(0): addrReg0 = load *fp(-50) // Two address registers with same value
> SU(1): addrReg1 = load *fp(-50)
> SU(2): store dataReg0:lo, *addrReg0(2) // Store a register in two
> parts
> SU(3): store dataReg0:hi, *addrReg0
> SU(4): dataReg1:lo = load *addrReg1(2) // Load a register in two parts
> SU(5): dataReg1:hi = load *addrReg1
>
> Since the addresses are loaded...