Displaying 3 results from an estimated 3 matches for "addrr_p".
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addrr_np
2012 Aug 01
3
[LLVMdev] TableGen related question for the Hexagon backend
Hi,
I'm looking for some suggestions on a problem related to the Hexagon
backend.
Hexagon architecture allows instructions in various formats. For example, we
have 3 variations of the add instruction as defined below:
ADDrr : r1 = add(r2, r3) --> add 2 32-bit registers ADDrr_p : if(p0) r1 =
add(r2, r3) --> predicated version of ADDrr instruction, executed when p0 is
true ADDrr_np : if(!p0) r1 = add(r2, r3) --> predicated version of ADDrr
instruction, executed when p0 is false
Currently, we rely on switch tables to transform between formats. However,
we would like...
2012 Aug 02
0
[LLVMdev] TableGen related question for the Hexagon backend
...'ThisInstr'.
>
> For example:
> class Relations {
> Instruction ThisInstr;
> Instruction BaseForm;
> Instruction TruePred;
> Instruction FalsePred;
> }
>
> def Rel_ADDrr : Relations<ADDrr, ADDrr, ADDrr_p, ADDrr_np>;
> def Rel_ADDrr_p: Relations<ADDrr_p, ADDrr, , >;
> def Rel_ADDrr_np : Relations<ADDrr_np,ADDrr, , >;
The problem is, this isn't really any better than having a large switch statement. You just moved the table into the .td file.
You should be taking advantage...
2012 Aug 16
2
[LLVMdev] TableGen related question for the Hexagon backend
...'ThisInstr'.
>
> For example:
> class Relations {
> Instruction ThisInstr;
> Instruction BaseForm;
> Instruction TruePred;
> Instruction FalsePred;
> }
>
> def Rel_ADDrr : Relations<ADDrr, ADDrr, ADDrr_p, ADDrr_np>; def
> Rel_ADDrr_p: Relations<ADDrr_p, ADDrr, , >; def Rel_ADDrr_np :
> Relations<ADDrr_np,ADDrr, , >;
The problem is, this isn't really any better than having a large switch
statement. You just moved the table into the .td file.
You should be taking advantag...