Displaying 3 results from an estimated 3 matches for "addrmodepc".
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addrmode
2010 Sep 07
0
[LLVMdev] MachineMemOperand and dependence information
...s were added to the newly generated instruction?
>
> (after optimization)
> %reg1054<def>, %reg1033<def> = LDRD %reg1030, %reg0, 264, pred:14, pred:%reg0; mem:LD4[%uglygep10], mem:LD4[%uglygep2021]
If I had to guess, I would think it's because of how LDR is defined:
def addrmodepc : Operand<i32>,
ComplexPattern<i32, 2, "SelectAddrModePC", []> {
let PrintMethod = "printAddrModePCOperand";
let MIOperandInfo = (ops GPR, i32imm);
}
def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
&...
2010 Sep 07
3
[LLVMdev] MachineMemOperand and dependence information
I have two questions regarding MachineMemOperands and dependence
information.
Q1) I noticed that MachineMemOperands are lost when two LDRs are combined
and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps.
(before optimization)
%reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0;
mem:LD4[%uglygep10]
%reg1054<def> = LDR %reg1030, %reg0, 4104, pred:14,
2010 Sep 07
1
[LLVMdev] MachineMemOperand and dependence information
...instruction?
> >
> > (after optimization)
> > %reg1054<def>, %reg1033<def> = LDRD %reg1030, %reg0, 264, pred:14,
> pred:%reg0; mem:LD4[%uglygep10], mem:LD4[%uglygep2021]
>
> If I had to guess, I would think it's because of how LDR is defined:
>
> def addrmodepc : Operand<i32>,
> ComplexPattern<i32, 2, "SelectAddrModePC", []> {
> let PrintMethod = "printAddrModePCOperand";
> let MIOperandInfo = (ops GPR, i32imm);
> }
> def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
> I...