Displaying 4 results from an estimated 4 matches for "addrmode4".
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addrmode
2010 Mar 19
2
[LLVMdev] Instruction with variable number of outputs
...ess format of the ARM ldm/stm instructions, a problem remains. The load multiple instruction looks like:
// A list of registers separated by comma. Used by load/store multiple.
def reglist : Operand<i32> {
let PrintMethod = "printRegisterList";
}
def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p,
reglist:$dsts, variable_ops),
IndexModeNone, LdStMulFrm, IIC_iLoadm,
"ldm${addr:submode}${p}\t$addr, $dsts", "", []>;
Tablegen produces an instruction description with 5 input operands: 2 for $addr,...
2010 Mar 19
2
[LLVMdev] Instruction with variable number of outputs
.... The load multiple instruction looks like:
>>
>> // A list of registers separated by comma. Used by load/store multiple.
>> def reglist : Operand<i32> {
>> let PrintMethod = "printRegisterList";
>> }
>>
>> def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p,
>> reglist:$dsts, variable_ops),
>> IndexModeNone, LdStMulFrm, IIC_iLoadm,
>> "ldm${addr:submode}${p}\t$addr, $dsts", "", []>;
>>
>> Tablegen produces an instruction descripti...
2010 Mar 19
0
[LLVMdev] Instruction with variable number of outputs
...ructions, a problem remains. The load multiple instruction looks like:
>
> // A list of registers separated by comma. Used by load/store multiple.
> def reglist : Operand<i32> {
> let PrintMethod = "printRegisterList";
> }
>
> def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p,
> reglist:$dsts, variable_ops),
> IndexModeNone, LdStMulFrm, IIC_iLoadm,
> "ldm${addr:submode}${p}\t$addr, $dsts", "", []>;
>
> Tablegen produces an instruction description
Ok, you mean...
2010 Mar 22
0
[LLVMdev] Instruction with variable number of outputs
...name without forcing the first operand to be an input.
Ok.
>>> def reglist : Operand<i32> {
>>> let PrintMethod = "printRegisterList";
>>> let MIOperandInfo = (ops variable_ops);
>>> }
>>>
>>> def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts),
>
> This syntax is not ideal, because reglist:$dsts is a variable list of output operands. But at least there is no extra input operand.
>
> I need a way of describing the LDM instruction with:
>
> Fixed outputs: none
> Fixed inputs: addr and...