search for: addrm

I'm writing a back-end for a target in which all dyadic instructions support one register and one memory operand but only some instructions support two register operations. For example ADDrm and ADDrr are supported, ANDrm is supported but ANDrr isn't. I've written descriptions for ADDrm, ADDrr and ANDrm in my InstrInfo.td file but instruction selection fails when presented with an AND that has two register operands, e.g. e = (a + b) & (c + d); I guess I need to force one...

On Mon, Jun 24, 2019 at 4:08 PM Tim Northover <t.p.northover at gmail.com> wrote: > On Mon, 24 Jun 2019 at 12:16, Gleb Popov via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > > 1. Where does it come from? Can I do anything to make it not appear? > > It comes from something like: > > %ptr = alloca i8 > %var = alloca i8* > store i8* %ptr, i8**

Hi all, I am trying to write a back-end for LLVM where any instruction may take any type of data. I am looking for the output to be of the format: inst.type reg1,reg2 etc. Where inst is the instruction, e.g. mov and type is data-type e.g. f32 etc. I tried creating a back-end with a register class which could take i32 and f32: def GPRegs : RegisterClass <"Test",

...us choice of > words. I wouldn't expect a load instruction on most architectures. > > > And what's "STORE"? Is it somehow different from "store"? > > On most targets in LLVM the implemented instruction names are written > in capital letters (mostly): ADDrm, MULrr, STRXrs. The STORE there was > meant to represent a target-specific store instruction (like you'd get > on the RHS of a Pat instantiation) without committing to any > particular architecture. > > Could you describe what *is* happening for you, BTW? Maybe with an > &quot...