Displaying 3 results from an estimated 3 matches for "addressregs".
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2008 Feb 18
0
[LLVMdev] More address registers
2008/2/15, Andreas Fredriksson <deplinenoise at gmail.com>:
>
> I tried mocking this up using the following. (Base is what's returned as
> the Ax in the move expression above when the DAG is constructed due to
> SelectAddr().)
>
> SDOperand chain = CurDAG->getCopyToReg(Base, M68K::A3, Base);
> Base = CurDAG->getCopyFromReg(chain, M68K::A3, MVT::i32);
2008 Feb 15
2
[LLVMdev] More address registers
Hi again,
I'm finally getting some time to work on my m68k backend again. :)
I was trying to solve the problem that loads from arbitrary addresses need
to go through address registers. 68k allows flexible addressing similar to
what the x86 can do, only that the adressing base has to reside in an
address register:
move.size[b/w/l] <Displacement>(Ax, Dx * Scale[1/2/4/8]), <Dest>
2014 Dec 05
2
[LLVMdev] illegal code generated for special architecture
...rameIndex to TargetFrameIndex (nothing special)
- I generate a special address-register ADD instruction in eliminateFrameIndex() to write FramePointer + offset into a new address-register
- I use explicit load and store and address-registers in my target instruction patterns:
eg (store (add (load AddressRegs:$a), DataRegs:$b), AddressRegs:$dst)
This works quite well, but if I access an array on the stack (LLVM generates FrameIndex to access it):
int buffer[BUFFER_SIZE];
for(int i = 0; i < end_loop_index; i++) {
buffer[i] = i;
}
then LLVM generates the target instruction "ADD D1,...