Displaying 20 results from an estimated 34 matches for "address_hi".
2012 Sep 11
1
[PATCH 3/3] VT-d: use msi_compose_msg()
...|= 1 << 14;
- msg.data |= (INT_DELIVERY_MODE != dest_LowestPrio) ?
- MSI_DATA_DELIVERY_FIXED:
- MSI_DATA_DELIVERY_LOWPRI;
-
- /* Follow MSI setting */
+ msi_compose_msg(desc, &msg);
+ /* Are these overrides really needed? */
if (x2apic_enabled)
msg.address_hi = dest & 0xFFFFFF00;
- msg.address_lo = (MSI_ADDRESS_HEADER << (MSI_ADDRESS_HEADER_SHIFT + 8));
- msg.address_lo |= INT_DEST_MODE ? MSI_ADDR_DESTMODE_LOGIC:
- MSI_ADDR_DESTMODE_PHYS;
- msg.address_lo |= (INT_DELIVERY_MODE != dest_LowestPrio) ?
-...
2014 Jul 04
2
How to check for proper MSI support?
...} else if (entry->msi_attrib.is_msix) {
> void __iomem *base;
> base = entry->mask_base +
> entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
>
> writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
> writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
> writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
> ......
>
>> shouldn't. I don't know all the details about MSI, but doesn't the CPU
>> or (L)APIC have to support it? In this case, it's a P200MMX on a 430FX
>...
2009 May 20
0
[PATCHv2-RFC 2/2] qemu-kvm: use common code for assigned msix
...urn;
}
- assigned_dev->entry->u.msi.address_lo =
+ assigned_dev->msi_entry->u.msi.address_lo =
*(uint32_t *)(pci_dev->config + pci_dev->cap.start +
PCI_MSI_ADDRESS_LO);
- assigned_dev->entry->u.msi.address_hi = 0;
- assigned_dev->entry->u.msi.data = *(uint16_t *)(pci_dev->config +
+ assigned_dev->msi_entry->u.msi.address_hi = 0;
+ assigned_dev->msi_entry->u.msi.data = *(uint16_t *)(pci_dev->config +
pci_dev->cap.start + PCI_MSI_DATA_32);
-...
2009 May 20
0
[PATCHv2-RFC 2/2] qemu-kvm: use common code for assigned msix
...urn;
}
- assigned_dev->entry->u.msi.address_lo =
+ assigned_dev->msi_entry->u.msi.address_lo =
*(uint32_t *)(pci_dev->config + pci_dev->cap.start +
PCI_MSI_ADDRESS_LO);
- assigned_dev->entry->u.msi.address_hi = 0;
- assigned_dev->entry->u.msi.data = *(uint16_t *)(pci_dev->config +
+ assigned_dev->msi_entry->u.msi.address_hi = 0;
+ assigned_dev->msi_entry->u.msi.data = *(uint16_t *)(pci_dev->config +
pci_dev->cap.start + PCI_MSI_DATA_32);
-...
2009 May 11
0
[PATCH 2/2] qemu-kvm: use common code for assigned msix
...urn;
}
- assigned_dev->entry->u.msi.address_lo =
+ assigned_dev->msi_entry->u.msi.address_lo =
*(uint32_t *)(pci_dev->config + pci_dev->cap.start +
PCI_MSI_ADDRESS_LO);
- assigned_dev->entry->u.msi.address_hi = 0;
- assigned_dev->entry->u.msi.data = *(uint16_t *)(pci_dev->config +
+ assigned_dev->msi_entry->u.msi.address_hi = 0;
+ assigned_dev->msi_entry->u.msi.data = *(uint16_t *)(pci_dev->config +
pci_dev->cap.start + PCI_MSI_DATA_32);
-...
2009 May 11
0
[PATCH 2/2] qemu-kvm: use common code for assigned msix
...urn;
}
- assigned_dev->entry->u.msi.address_lo =
+ assigned_dev->msi_entry->u.msi.address_lo =
*(uint32_t *)(pci_dev->config + pci_dev->cap.start +
PCI_MSI_ADDRESS_LO);
- assigned_dev->entry->u.msi.address_hi = 0;
- assigned_dev->entry->u.msi.data = *(uint16_t *)(pci_dev->config +
+ assigned_dev->msi_entry->u.msi.address_hi = 0;
+ assigned_dev->msi_entry->u.msi.data = *(uint16_t *)(pci_dev->config +
pci_dev->cap.start + PCI_MSI_DATA_32);
-...
2014 Jul 04
0
How to check for proper MSI support?
...;msi_attrib.is_msix) {
>> void __iomem *base;
>> base = entry->mask_base +
>> entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
>>
>> writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
>> writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
>> writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
>> ......
>>
>>> shouldn't. I don't know all the details about MSI, but doesn't the CPU
>>> or (L)APIC have to support it? In this case, it's a P2...
2015 Oct 09
4
[PATCH 1/2] kvm/x86: Hyper-V synthetic interrupt controller
...rn kvm_hv_synic_set_irq(kvm, e->hv_sint.vcpu, e->hv_sint.sint);
> +}
>
> static int kvm_set_msi_inatomic(struct kvm_kernel_irq_routing_entry *e,
> struct kvm *kvm)
> @@ -289,6 +300,11 @@ int kvm_set_routing_entry(struct kvm_kernel_irq_routing_entry *e,
> e->msi.address_hi = ue->u.msi.address_hi;
> e->msi.data = ue->u.msi.data;
> break;
> + case KVM_IRQ_ROUTING_HV_SINT:
> + e->set = kvm_hv_set_sint;
> + e->hv_sint.vcpu = ue->u.hv_sint.vcpu;
> + e->hv_sint.sint = ue->u.hv_sint.sint;
> + break;
> default:
>...
2015 Oct 09
4
[PATCH 1/2] kvm/x86: Hyper-V synthetic interrupt controller
...rn kvm_hv_synic_set_irq(kvm, e->hv_sint.vcpu, e->hv_sint.sint);
> +}
>
> static int kvm_set_msi_inatomic(struct kvm_kernel_irq_routing_entry *e,
> struct kvm *kvm)
> @@ -289,6 +300,11 @@ int kvm_set_routing_entry(struct kvm_kernel_irq_routing_entry *e,
> e->msi.address_hi = ue->u.msi.address_hi;
> e->msi.data = ue->u.msi.data;
> break;
> + case KVM_IRQ_ROUTING_HV_SINT:
> + e->set = kvm_hv_set_sint;
> + e->hv_sint.vcpu = ue->u.hv_sint.vcpu;
> + e->hv_sint.sint = ue->u.hv_sint.sint;
> + break;
> default:
>...
2015 Oct 09
5
[PATCH 0/2] Hyper-V synthetic interrupt controller
This patchset implements the KVM part of the synthetic interrupt
controller (synic) which is a building block of the Hyper-V
paravirtualized device bus (vmbus).
Synic is a lapic extension, which is controlled via MSRs and maintains
for each vCPU
- 16 synthetic interrupt "lines" (SINT's); each can be configured to
trigger a specific interrupt vector optionally with auto-EOI
2015 Oct 09
5
[PATCH 0/2] Hyper-V synthetic interrupt controller
This patchset implements the KVM part of the synthetic interrupt
controller (synic) which is a building block of the Hyper-V
paravirtualized device bus (vmbus).
Synic is a lapic extension, which is controlled via MSRs and maintains
for each vCPU
- 16 synthetic interrupt "lines" (SINT's); each can be configured to
trigger a specific interrupt vector optionally with auto-EOI
2015 Oct 09
0
[PATCH 1/2] kvm/x86: Hyper-V synthetic interrupt controller
...!level)
+ return -1;
+
+ return kvm_hv_synic_set_irq(kvm, e->hv_sint.vcpu, e->hv_sint.sint);
+}
static int kvm_set_msi_inatomic(struct kvm_kernel_irq_routing_entry *e,
struct kvm *kvm)
@@ -289,6 +300,11 @@ int kvm_set_routing_entry(struct kvm_kernel_irq_routing_entry *e,
e->msi.address_hi = ue->u.msi.address_hi;
e->msi.data = ue->u.msi.data;
break;
+ case KVM_IRQ_ROUTING_HV_SINT:
+ e->set = kvm_hv_set_sint;
+ e->hv_sint.vcpu = ue->u.hv_sint.vcpu;
+ e->hv_sint.sint = ue->u.hv_sint.sint;
+ break;
default:
goto out;
}
diff --git a/arch/x86/kvm/l...
2014 Jul 26
0
[RFC PATCH 09/11] PCI/MSI: refactor PCI MSI driver
...urrent_state != PCI_D0);
+ struct pci_dev *dev = entry->msi->data;
+
+ BUG_ON(dev->current_state != PCI_D0);
if (entry->msi_attrib.is_msix) {
void __iomem *base = entry->mask_base +
@@ -271,7 +294,6 @@ void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
} else {
- struct pci_dev *dev = entry->dev;
int pos = dev->msi_cap;
u16 data;
@@ -315,7 +337,9 @@ void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
void __write_msi_msg(...
2014 Aug 20
1
[RFC PATCH 09/11] PCI/MSI: refactor PCI MSI driver
...ev *dev = entry->msi->data;
> +
> + BUG_ON(dev->current_state != PCI_D0);
>
> if (entry->msi_attrib.is_msix) {
> void __iomem *base = entry->mask_base +
> @@ -271,7 +294,6 @@ void __read_msi_msg(struct msi_desc *entry, struct msi_msg
> *msg)
> msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
> msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
> } else {
> - struct pci_dev *dev = entry->dev;
> int pos = dev->msi_cap;
> u16 data;
>
> @@ -315,7 +337,9 @@ void get_cached_msi_msg(unsigned int irq, struct msi_...
2014 Aug 20
1
[RFC PATCH 09/11] PCI/MSI: refactor PCI MSI driver
...ev *dev = entry->msi->data;
> +
> + BUG_ON(dev->current_state != PCI_D0);
>
> if (entry->msi_attrib.is_msix) {
> void __iomem *base = entry->mask_base +
> @@ -271,7 +294,6 @@ void __read_msi_msg(struct msi_desc *entry, struct msi_msg
> *msg)
> msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
> msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
> } else {
> - struct pci_dev *dev = entry->dev;
> int pos = dev->msi_cap;
> u16 data;
>
> @@ -315,7 +337,9 @@ void get_cached_msi_msg(unsigned int irq, struct msi_...
2014 Jul 26
0
[RFC PATCH 10/11] PCI/MSI: Split the generic MSI code into new file
...t msi_msg *msg)
+{
+ struct msi_desc *entry = irq_get_msi_desc(irq);
+
+ __read_msi_msg(entry, msg);
+}
+
+void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
+{
+ /* Assert that the cache is valid, assuming that
+ * valid messages are not all-zeroes. */
+ BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo |
+ entry->msg.data));
+
+ *msg = entry->msg;
+}
+
+void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
+{
+ struct msi_desc *entry = irq_get_msi_desc(irq);
+
+ __get_cached_msi_msg(entry, msg);
+}
+
+void __write_msi_msg(struct msi_desc *entry, struct...
2014 Aug 20
1
[RFC PATCH 10/11] PCI/MSI: Split the generic MSI code into new file
...irq_get_msi_desc(irq);
> +
> + __read_msi_msg(entry, msg);
> +}
> +
> +void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
> +{
> + /* Assert that the cache is valid, assuming that
> + * valid messages are not all-zeroes. */
> + BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo |
> + entry->msg.data));
> +
> + *msg = entry->msg;
> +}
> +
> +void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
> +{
> + struct msi_desc *entry = irq_get_msi_desc(irq);
> +
> + __get_cached_msi_msg(entry, msg);
> +}...
2014 Aug 20
1
[RFC PATCH 10/11] PCI/MSI: Split the generic MSI code into new file
...irq_get_msi_desc(irq);
> +
> + __read_msi_msg(entry, msg);
> +}
> +
> +void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
> +{
> + /* Assert that the cache is valid, assuming that
> + * valid messages are not all-zeroes. */
> + BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo |
> + entry->msg.data));
> +
> + *msg = entry->msg;
> +}
> +
> +void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
> +{
> + struct msi_desc *entry = irq_get_msi_desc(irq);
> +
> + __get_cached_msi_msg(entry, msg);
> +}...
2014 Jul 04
4
How to check for proper MSI support?
...gt;>> void __iomem *base;
>>> base = entry->mask_base +
>>> entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
>>>
>>> writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
>>> writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
>>> writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
>>> ......
>>>
>>>> shouldn't. I don't know all the details about MSI, but doesn't the CPU
>>>> or (L)APIC have to support it? In this...
2015 Oct 16
10
[PATCH v2 0/9] Hyper-V synthetic interrupt controller
This patchset implements the KVM part of the synthetic interrupt
controller (SynIC) which is a building block of the Hyper-V
paravirtualized device bus (vmbus).
SynIC is a lapic extension, which is controlled via MSRs and maintains
for each vCPU
- 16 synthetic interrupt "lines" (SINT's); each can be configured to
trigger a specific interrupt vector optionally with auto-EOI