search for: addregfrm

I am new to the LLVM backends, I am wondering how instruction selection is done in LLVM backends, I looked at the .td files in Target/X86, they all seem to be small and do not deal with common X86 instructions, i.e. mov, push, pop, etc. Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL:

...I used was: 1. Find an unused opcode, e.g. 0xF1 in this table: http://ref.x86asm.net/coder32.html 2. Insert an instruction into lib/Target/X86/X86InstrInfo.td using this opcode. In this case, I used 0xF1, and created the following instruction: def CACHE_OPERAND_B64i : RIi64<0xF1, AddRegFrm, (outs GR64:$unused), (ins i64imm:$b), "cache_operand_b_i64\t$b", [(int_cache_operand_b_i64 i64imm:$b)]>, Requires<[In64BitMode]>; However, when I compile, I'm getting errors of the form: Error: Primary decode conflict: TEST64...

...only need to implement GetFunctionSize for X86 and that's not as horrible as you think it is. For each instruction: 1. Compute how many bytes of prefix. The code is there in X86CodeEmitter except all you need is the size, not the prefixes being emitted. 2. For each instruction format, e.g AddRegFrm, MRMDestReg, it's either only one single byte for opcode or one additional ModR/M byte. Again, all the information is right there. 3. Some memory instructions needs a SIB byte. 4. Process the operands! Some special handling for operands that made up of the memory address. But the logic is...

...Forms ----- Pseudo - No encoding/disassembling information is present. These should be removed/replaced with other instructions before we reach the encoding phase of codegen.; RawFrm - Instruction has no modrm byte. Operands are fixed registers. There may be an immediate present. AddRegFrm - Instruction encodes a register in bits 2:0 of the opcode. No modrm byte. Opcode should be a multiple of 8 for such an instruction. RawFrmMemOffs - Instruction encodes a fixed constant address in the instruction without modrm byte. Basically opcodes 0xA0-0xA3 RawFrmSrc - Instruction u...

I am attempting to create an instruction which takes a single 64-bit immediate. This doesn't seem like a thing that would exist already (because who needs an instruction which just takes an immediate?) How might I implement this easily? Perhaps I could use a format which encodes a register, which is then unused? Thanks for the help. Gus -------------- next part -------------- An HTML

Evan Cheng wrote: > On Apr 1, 2008, at 12:50 AM, Nicolas Geoffray wrote: > > > That's a hack. :-) It is if you think that code emitter should only be used for actually writing somewhere the data. It is not if you find it another useful utility ;-) > Some targets already have ways to compute the exact > size of a function. See ARM::GetFunctionSize()

...tFunctionSize for X86 and that's > not as horrible as you think it is. For each instruction: > 1. Compute how many bytes of prefix. The code is there in > X86CodeEmitter except all you need is the size, not the prefixes being > emitted. > 2. For each instruction format, e.g AddRegFrm, MRMDestReg, it's either > only one single byte for opcode or one additional ModR/M byte. Again, > all the information is right there. > 3. Some memory instructions needs a SIB byte. > 4. Process the operands! Some special handling for operands that made > up of the memory...

...that's >> not as horrible as you think it is. For each instruction: >> 1. Compute how many bytes of prefix. The code is there in >> X86CodeEmitter except all you need is the size, not the prefixes >> being >> emitted. >> 2. For each instruction format, e.g AddRegFrm, MRMDestReg, it's >> either >> only one single byte for opcode or one additional ModR/M byte. Again, >> all the information is right there. >> 3. Some memory instructions needs a SIB byte. >> 4. Process the operands! Some special handling for operands that made &...

...SymbolAddress(false); > + } else if (MO.isImmediate()) { > + FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); > + } else { > + assert(0 && "Unknown RawFrm operand!"); > + } > + } > + break; > + > + case X86II::AddRegFrm: > + ++FinalSize; > + > + if (CurOp != NumOps) { > + const MachineOperand &MO1 = MI.getOperand(CurOp++); > + unsigned Size = X86InstrInfo::sizeOfImm(Desc); > + if (MO1.isImmediate()) > + FinalSize += sizeConstant(Size); > + else { > +...

OK, here's a new patch that adds the infrastructure and the implementation for X86, ARM and PPC of GetInstSize and GetFunctionSize. Both functions are virtual functions defined in TargetInstrInfo.h. For X86, I moved some commodity functions from X86CodeEmitter to X86InstrInfo. What do you think? Nicolas Evan Cheng wrote: > > I think both of these belong to TargetInstrInfo. And