search for: addrbasereg

...load” MachineInstrs will have multiple operands, ex: > %5 = MOV64rm %0, 1, $noreg, 0, $noreg and in order to know which operand is what, the X86 backend uses some enums and helper functions so that they can write code like: > const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); > const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); for both MachineInstrs and MCInsts. > > Is it possible to have a X86 MachineInstr with a memory operand (i.e. X86II::getMemoryOperandNo >=0), that has no MachineMemOperand? What about the reverse? > * Attac...

Hello, I'm trying to understand the relationship between MachineMemOperand and, on X86, memory operands of machine instructions. The latter seem to be operands held in order by the MachineInstr, from an offset onwards - Base, Scale, Index, Displacement, Segment. The former, if I understand it correctly, is used to hold a relationship back to IR load/store instructions. Is it possible to have

...ple operands, ex: > > > %5 = MOV64rm %0, 1, $noreg, 0, $noreg > > > and in order to know which operand is what, the X86 backend uses some > enums and helper functions so that they can write code like: > > > const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); > > > const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); > > for both MachineInstrs and MCInsts. > > > > > Is it possible to have a X86 MachineInstr with a memory operand (i.e. > X86II::getMemoryOperandNo >=0), that has no MachineMemOperand? Wh...

Hi, I would like to query the X86InstrInfo tables to determine if a given opcode is a load or store from stack. I see functions isFrameLoadOpcode and isFrameStoreOpcode in lib/Target/X86/X86InstrInfo.cpp that would provide the functionality I am looking for. However, these functions are static. What is the recommended way to perform such queries for a MachineInstr - short of replicating the