Displaying 7 results from an estimated 7 matches for "addr_mask".
2015 Apr 13
3
[PATCH v4] pmu/gk20a: PMU boot support
...mc_enable & 0x2000) != 0x0) {
+ gk20a_pmu_enable_irq(priv, pmc, false);
+ gk20a_pmu_enable_hw(priv, pmc, false);
+ }
+ }
+
+ return 0;
+}
+
+static void
+gk20a_pmu_copy_to_dmem(struct gk20a_pmu_priv *priv, u32 dst, u8 *src, u32 size,
+ u8 port)
+{
+ u32 i, words, bytes;
+ u32 data, addr_mask;
+ u32 *src_u32 = (u32 *)src;
+
+ if (size == 0) {
+ nv_error(priv, "size is zero\n");
+ goto out;
+ }
+
+ if (dst & 0x3) {
+ nv_error(priv, "dst (0x%08x) not 4-byte aligned\n", dst);
+ goto out;
+ }
+
+ mutex_lock(&priv->pmu_copy_lock);
+ words = size >> 2;...
2015 Apr 08
3
[PATCH V2] pmu/gk20a: PMU boot support.
...hw mutex */
+
+ err = pmu_enable(ppmu, pmc, false);
+ if (err)
+ return err;
+
+ err = pmu_enable(ppmu, pmc, true);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+static void
+pmu_copy_to_dmem(struct gk20a_pmu_priv *pmu,
+ u32 dst, u8 *src, u32 size, u8 port)
+{
+ u32 i, words, bytes;
+ u32 data, addr_mask;
+ u32 *src_u32 = (u32 *)src;
+ struct nvkm_pmu *ppmu = &pmu->base;
+
+ if (size == 0) {
+ nv_error(ppmu, "size is zero\n");
+ goto out;
+ }
+
+ if (dst & 0x3) {
+ nv_error(ppmu, "dst (0x%08x) not 4-byte aligned\n", dst);
+ goto out;
+ }
+
+ mutex_lock(&pmu-&g...
2015 Apr 30
2
[PATCH v4] pmu/gk20a: PMU boot support
...>> +
>> + return 0;
>> +}
>> +
>> +static void
>> +gk20a_pmu_copy_to_dmem(struct gk20a_pmu_priv *priv, u32 dst, u8 *src, u32
>> size,
>> + u8 port)
>> +{
>> + u32 i, words, bytes;
>> + u32 data, addr_mask;
>> + u32 *src_u32 = (u32 *)src;
>> +
>> + if (size == 0) {
>> + nv_error(priv, "size is zero\n");
>> + goto out;
>> + }
>> +
>> + if (dst & 0x3) {
>> + nv_error(pri...
2012 Sep 26
3
[PATCH v3] xen/tools: Add 64 bits big bar support
..., &edx);
+ if ( eax >= 0x80000008 )
+ {
+ cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
+ phys_bits = (uint8_t)eax;
+ }
+
+ return phys_bits;
+}
+
void cacheattr_init(void)
{
uint32_t eax, ebx, ecx, edx;
uint64_t mtrr_cap, mtrr_def, content, addr_mask;
- unsigned int i, nr_var_ranges, phys_bits = 36;
+ unsigned int i, nr_var_ranges, phys_bits;
/* Does the CPU support architectural MTRRs? */
cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
if ( !(edx & (1u << 12)) )
return;
- /* Find the p...
2015 Mar 11
0
[PATCH] pmu/gk20a: PMU boot support.
...u_fini,
> },
> + .base.handle = NV_SUBDEV(PMU, 0xea),
> + .pgob = gk20a_pmu_pgob,
> }.base;
> +void pmu_copy_from_dmem(struct pmu_desc *pmu,
> + u32 src, u8 *dst, u32 size, u8 port)
> +{
> + u32 i, words, bytes;
> + u32 data, addr_mask;
> + u32 *dst_u32 = (u32 *)dst;
> + struct nvkm_pmu *ppmu = (void *)nvkm_pmu((void *)
> + impl_from_pmu(pmu));
> +
> + if (size == 0) {
> + nv_error(ppmu, "size is zero\n");
> + goto out;
> + }
>...
2015 Mar 11
3
[PATCH] pmu/gk20a: PMU boot support.
...mu_oclass = &(struct nvkm_pmu_impl) {
.init = gk20a_pmu_init,
.fini = gk20a_pmu_fini,
},
+ .base.handle = NV_SUBDEV(PMU, 0xea),
+ .pgob = gk20a_pmu_pgob,
}.base;
+void pmu_copy_from_dmem(struct pmu_desc *pmu,
+ u32 src, u8 *dst, u32 size, u8 port)
+{
+ u32 i, words, bytes;
+ u32 data, addr_mask;
+ u32 *dst_u32 = (u32 *)dst;
+ struct nvkm_pmu *ppmu = (void *)nvkm_pmu((void *)
+ impl_from_pmu(pmu));
+
+ if (size == 0) {
+ nv_error(ppmu, "size is zero\n");
+ goto out;
+ }
+
+ if (src & 0x3) {
+ nv_error(ppmu, "src (0x%08x) not 4-byte aligned\n", src);
+ goto out;...
2015 Mar 12
2
[PATCH] pmu/gk20a: PMU boot support.
...u_fini,
> },
> + .base.handle = NV_SUBDEV(PMU, 0xea),
> + .pgob = gk20a_pmu_pgob,
> }.base;
> +void pmu_copy_from_dmem(struct pmu_desc *pmu,
> + u32 src, u8 *dst, u32 size, u8 port)
> +{
> + u32 i, words, bytes;
> + u32 data, addr_mask;
> + u32 *dst_u32 = (u32 *)dst;
> + struct nvkm_pmu *ppmu = (void *)nvkm_pmu((void *)
> + impl_from_pmu(pmu));
> +
> + if (size == 0) {
> + nv_error(ppmu, "size is zero\n");
> + goto out;
> + }
>...