search for: addr_data

...t = nvkm_gpuobj_map_vm(nv_gpuobj(priv->trace_buf.obj), pmuvm->vm, + NV_MEM_ACCESS_RW, &priv->trace_buf.vma); + if (ret) + return ret; + + return 0; +} + +static int +gk20a_pmu_bootstrap(struct gk20a_pmu_priv *priv) +{ + struct pmu_ucode_desc *desc = priv->desc; + u32 addr_code, addr_data, addr_load; + u32 i, blocks, addr_args; + struct pmu_cmdline_args_gk20a cmdline_args; + struct nvkm_pmu_priv_vm *pmuvm = &priv->pmuvm; + + nv_mask(priv, 0x0010a048, 0x01, 0x01); + /*bind the address*/ + nv_wr32(priv, 0x0010a480, + pmuvm->mem->addr >> 12 | + 0x1 << 30 | +...

...+ pmu->sw_ready = true; + +skip_init: + return 0; +map_err: + nvkm_gpuobj_destroy(pmu->trace_buf.obj); +err: + return err; +} + +static int +pmu_bootstrap(struct gk20a_pmu_priv *pmu) +{ + struct nvkm_pmu *ppmu = &pmu->base; + struct pmu_ucode_desc *desc = pmu->desc; + u32 addr_code, addr_data, addr_load; + u32 i, blocks, addr_args; + struct pmu_cmdline_args_gk20a cmdline_args; + struct nvkm_pmu_priv_vm *ppmuvm = &pmu->pmuvm; + nv_mask(ppmu, 0x0010a048, 0x01, 0x01); + /*bind the address*/ + nv_wr32(ppmu, 0x0010a480, + ppmuvm->mem->addr >> 12 | + 0x1 << 30 | +...

...if (ret) >> + return ret; >> + >> + return 0; >> +} >> + >> +static int >> +gk20a_pmu_bootstrap(struct gk20a_pmu_priv *priv) >> +{ >> + struct pmu_ucode_desc *desc = priv->desc; >> + u32 addr_code, addr_data, addr_load; >> + u32 i, blocks, addr_args; >> + struct pmu_cmdline_args_gk20a cmdline_args; >> + struct nvkm_pmu_priv_vm *pmuvm = &priv->pmuvm; >> + >> + nv_mask(priv, 0x0010a048, 0x01, 0x01); >> + /*bind the address*/ >&gt...

Sending things in a smaller chunks since it makes their reviewing easier. This part part 2/3 of the secboot refactoring/PMU command support patch series. Part 1 was the new falcon library which should be merged soon now. This series is mainly a refactoring/sanitization of the existing secure boot code. It does not add new features (part 3 will). Secure boot handling is now separated by NVIDIA

...wpr_addr, void *_desc) { + struct ls_ucode_img_r352 *img = ls_ucode_img_r352(_img); struct acr_r352_flcn_bl_desc *desc = _desc; - const struct ls_ucode_img_desc *pdesc = &img->ucode_desc; + const struct ls_ucode_img_desc *pdesc = &_img->ucode_desc; u64 base, addr_code, addr_data; base = wpr_addr + img->lsb_header.ucode_off + pdesc->app_start_offset; @@ -162,29 +162,46 @@ struct hsflcn_acr_desc { * Low-secure blob creation */ -typedef int (*lsf_load_func)(const struct nvkm_subdev *, struct ls_ucode_img *); - /** * ls_ucode_img_load() - create a lsf_ucode_...

This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

...rr; > + > + return 0; > +} > + > +static int pmu_bootstrap(struct pmu_desc *pmu) > +{ > + struct nvkm_pmu *ppmu = (void *)nvkm_pmu((void *) > + impl_from_pmu(pmu)); > + struct pmu_ucode_desc *desc = pmu->desc; > + u64 addr_code, addr_data, addr_load; > + u32 i, blocks, addr_args; > + u32 *adr_data, *adr_load, *adr_code; > + struct pmu_cmdline_args_gk20a cmdline_args; > + struct pmu_priv_vm *ppmuvm = &pmuvm; > + > + nv_wr32(ppmu, 0x0010a048, > + nv_rd32(ppmu, 0x0010...

...+ if (err) + return err; + + err = pmu_enable(ppmu, pmc, true); + if (err) + return err; + + return 0; +} + +static int pmu_bootstrap(struct pmu_desc *pmu) +{ + struct nvkm_pmu *ppmu = (void *)nvkm_pmu((void *) + impl_from_pmu(pmu)); + struct pmu_ucode_desc *desc = pmu->desc; + u64 addr_code, addr_data, addr_load; + u32 i, blocks, addr_args; + u32 *adr_data, *adr_load, *adr_code; + struct pmu_cmdline_args_gk20a cmdline_args; + struct pmu_priv_vm *ppmuvm = &pmuvm; + + nv_wr32(ppmu, 0x0010a048, + nv_rd32(ppmu, 0x0010a048) | 0x01); + /*bind the address*/ + nv_wr32(ppmu, 0x0010a480, + ppmuvm-&g...

...rr; > + > + return 0; > +} > + > +static int pmu_bootstrap(struct pmu_desc *pmu) > +{ > + struct nvkm_pmu *ppmu = (void *)nvkm_pmu((void *) > + impl_from_pmu(pmu)); > + struct pmu_ucode_desc *desc = pmu->desc; > + u64 addr_code, addr_data, addr_load; > + u32 i, blocks, addr_args; > + u32 *adr_data, *adr_load, *adr_code; > + struct pmu_cmdline_args_gk20a cmdline_args; > + struct pmu_priv_vm *ppmuvm = &pmuvm; > + > + nv_wr32(ppmu, 0x0010a048, > + nv_rd32(ppmu, 0x0010...