Displaying 20 results from an estimated 57 matches for "addr1".
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2006 Jan 27
2
Trying to understand the difference between similar iterators
What''s the difference between these two?
Objective:
Trying to display the addresses of the students that has "has_many"
relations with addresses
<td><% @student.addresses.each {|address| "Address:
#{address.addr1}<br/>"} %> </td> ****** did not work
<% end %>
This code worked:
<td><% @student.addresses.each do |address|%>
<%= address.addr1 %><br/>
<% end %>
Any comments appreciated.
Thanks
Silvy Mathews
2008 Dec 15
2
Duplicates among columns of a data frame
Dear list,
I have a data frame of survey respondents, a little like this:
set.seed(20081215)
n <- 100
dat <- data.frame(id=1:100,
addr1=sample(LETTERS, n, replace=TRUE),
addr2=sample(LETTERS, n, replace=TRUE),
addr3=sample(LETTERS, n, replace=TRUE))
head(dat)
id addr1 addr2 addr3
1 1 R H Q
2 2 H C K
3 3 I P S
4 4 A H L
5 5 P Q...
2006 Jan 28
2
Trying to understand the difference between similariterators
...u''re iterating through a block, you don''t need
to have an end. In fact it should give you some kind of error.
Secondly, <% just evals a statement, <%= renders the output. So your
loop should be:
<td><%= @student.addresses.each {|address| "Address:
#{address.addr1}<br/>"} %> </td>
Pat
On 1/27/06, Silvy@funmail.com <Silvy@funmail.com> wrote:
> What''s the difference between these two?
> Objective:
> Trying to display the addresses of the students that has "has_many"
> relations with addresses
>
&g...
2011 Nov 02
2
[LLVMdev] annotations preventing optimizations/cleanup?
...ent code then when I
use the source directly. In both cases I'm compiling with -O4. Can
anyone explain this?
Thanks
define i32 @somefunc(i32 (i32)* %ptr) nounwind uwtable {
entry:
%ptr.addr = alloca i32 (i32)*, align 8
store i32 (i32)* %ptr, i32 (i32)** %ptr.addr, align 8, !tbaa !0
%ptr.addr1 = bitcast i32 (i32)** %ptr.addr to i8*
call void @llvm.var.annotation(i8* %ptr.addr1, i8* getelementptr
inbounds ([11 x i8]* @.str, i64 0, i64 0), i8* getelementptr inbounds
([51 x i8]* @.str1, i64 0, i64 0), i32 13)
%0 = load i32 (i32)** %ptr.addr, align 8, !tbaa !0
%cmp = icmp eq i32 (i32)*...
2006 Jan 09
3
Design Question
...to this. This is more
towards the database design for the scenario below:
Say for example,
I have a person table and this person can have different address types.
One could be Home and the other could be say Office.
Should be model this
Table people
id
fname
lname
Table addresses
id
person_id
addr1
addr2
....
or
Table people
id
fname
lname
Table addresses
id
addr1
addr2
Table persons_addresses
person_id
address_id
Are there any tutorial that explains these concepts?
Any help is highly appreciated.
Thanks
Silvy Mathews
-------------- next part --------------
An HTML attac...
2015 Mar 12
1
[PATCH 1/2] pbus/hwsq: Support strided register writes
...mask;
u32 data;
};
static inline struct hwsq_reg
+hwsq_stride(u32 addr, u32 stride, u32 mask)
+{
+ return (struct hwsq_reg) {
+ .sequence = 0,
+ .force = 0,
+ .addr = addr,
+ .stride = stride,
+ .mask = mask,
+ .data = 0xdeadbeef,
+ };
+}
+
+static inline struct hwsq_reg
hwsq_reg2(u32 addr1, u32 addr2)
{
return (struct hwsq_reg) {
.sequence = 0,
.force = 0,
- .addr = { addr1, addr2 },
+ .addr = addr1,
+ .stride = addr2 - addr1,
+ .mask = 0x3,
.data = 0xdeadbeef,
};
}
@@ -29,7 +46,14 @@ hwsq_reg2(u32 addr1, u32 addr2)
static inline struct hwsq_reg
hwsq_reg(u32 addr...
2008 Sep 06
0
Tab control using FXRuby
...|LAYOUT_FILL_Y)
fld3= FXDataTarget.new("")
FXTextField.new(addr,20, fld3, FXDataTarget::ID_VALUE,
FRAME_SUNKEN|LAYOUT_FILL_X|LAYOUT_FILL_Y)
fld3.connect(SEL_COMMAND) do
puts "fld3 contains #{fld3.value}"
main.setPosition(-30, -30)
end
FXLabel.new(addr, "Addr1" , nil,LABEL_NORMAL|LAYOUT_FILL_X|LAYOUT_FILL_Y)
addr1= FXDataTarget.new("")
FXTextField.new(addr,20, addr1, FXDataTarget::ID_VALUE,
FRAME_SUNKEN|LAYOUT_FILL_X|LAYOUT_FILL_Y)
addr1.connect(SEL_COMMAND) do
puts "addr1 contains #{addr1.value}"
main.setPosition...
2011 Nov 02
0
[LLVMdev] annotations preventing optimizations/cleanup?
...lements annotations on local variables, that's all.
Ciao, Duncan.
>
> Thanks
>
> define i32 @somefunc(i32 (i32)* %ptr) nounwind uwtable {
> entry:
> %ptr.addr = alloca i32 (i32)*, align 8
> store i32 (i32)* %ptr, i32 (i32)** %ptr.addr, align 8, !tbaa !0
> %ptr.addr1 = bitcast i32 (i32)** %ptr.addr to i8*
> call void @llvm.var.annotation(i8* %ptr.addr1, i8* getelementptr
> inbounds ([11 x i8]* @.str, i64 0, i64 0), i8* getelementptr inbounds
> ([51 x i8]* @.str1, i64 0, i64 0), i32 13)
> %0 = load i32 (i32)** %ptr.addr, align 8, !tbaa !0
>...
2016 Mar 11
3
masked-load endpoints optimization
...have is whether it is legal to read the extra memory,
regardless of whether this is a masked load or something else.
Note that the x86 backend already does this, so either my proposal is ok
for x86, or we're already doing an illegal optimization:
define <4 x i32> @load_bonus_bytes(i32* %addr1, <4 x i32> %v) {
%ld1 = load i32, i32* %addr1
%addr2 = getelementptr i32, i32* %addr1, i64 3
%ld2 = load i32, i32* %addr2
%vec1 = insertelement <4 x i32> undef, i32 %ld1, i32 0
%vec2 = insertelement <4 x i32> %vec1, i32 %ld2, i32 3
ret <4 x i32> %vec2
}
$ ./llc...
2011 Oct 07
2
[LLVMdev] MIPS 32bit code generation
...> Do you want to replace
>
> lui $2, %hi(g1)
> addiu $2, $2, %lo(g1)
>
> with this?
> la $2, g1
>
> If that is the case, you can add this pattern.
>
> def op_la : Operand<i32>;
>
> def LA :
> FI<0x09, (outs CPURegs:$dst), (ins op_la:$addr0, op_la:$addr1),
> "la $dst, $addr0", [(set CPURegs:$dst,
> (add (MipsHi tglobaladdr:$addr0), (MipsLo
> tglobaladdr:$addr1)))], IIAlu>;
>
> Note that you still need to find a way to print "g1" instead of "%hi(g1)".
>
> On Wed, Oct 5...
2009 Dec 12
1
Dovecot-sieve multiple redirect question
Hi,
I have a question about redirecting message to a multiple addresses.
I have an user script like following:
require ["copy"];
redirect :copy "addr1 at dom.ain";
redirect :copy "addr2 at dom.ain";
All works fine, but if addr1 at ... has exceeded quota, this script seems stop
working and addr2 at ... doesn't receive this message too.
Is this correct behaviour?
How to avoid this?
Thanks,
Kryol
2014 Feb 28
1
VoiceMail Issue
Hello,
am attempting again to resolve an issue with multi-tenancy and the forwarding to VMs between mailboxes. If in a multi-tenancy environment one uses custom contexts ie.
[a1-ext1](a1)
mailbox=101 at a1
and the associated voicemail.conf entry:
[a1]
101 => 1234,My User 1,addr1 at email.com,,tz=eastern|imapuser=addr1 at email.com|imapfolder=Inbox
102 => 1234,My User 2,addr2 at email.com,,tz=eastern|imapuser=addr2 at email.com|imapfolder=Inbox
now if a message is left in mailbox 101 and the user attempts to forward the message to mailbox 102 Asterisk responds that mail...
2020 Nov 03
0
[patch V3 25/37] mm/highmem: Provide kmap_local*
...*
- * Side effect: On return pagefaults and preemption are disabled.
- *
* Can be invoked from any context.
*
* Requires careful handling when nesting multiple mappings because the map
* management is stack based. The unmap has to be in the reverse order of
* the map operation:
*
- * addr1 = kmap_atomic(page1);
- * addr2 = kmap_atomic(page2);
+ * addr1 = kmap_local_page(page1);
+ * addr2 = kmap_local_page(page2);
* ...
- * kunmap_atomic(addr2);
- * kunmap_atomic(addr1);
+ * kunmap_local(addr2);
+ * kunmap_local(addr1);
*
* Unmapping addr1 before addr2 is invalid and causes malf...
2011 Oct 06
0
[LLVMdev] MIPS 32bit code generation
Do you want to replace
lui $2, %hi(g1)
addiu $2, $2, %lo(g1)
with this?
la $2, g1
If that is the case, you can add this pattern.
def op_la : Operand<i32>;
def LA :
FI<0x09, (outs CPURegs:$dst), (ins op_la:$addr0, op_la:$addr1),
"la $dst, $addr0", [(set CPURegs:$dst,
(add (MipsHi tglobaladdr:$addr0), (MipsLo
tglobaladdr:$addr1)))], IIAlu>;
Note that you still need to find a way to print "g1" instead of "%hi(g1)".
On Wed, Oct 5, 2011 at 4:01 PM, Gang-Ryung U...
2011 Oct 07
0
[LLVMdev] MIPS 32bit code generation
...Do you want to replace
>
> lui $2, %hi(g1)
> addiu $2, $2, %lo(g1)
>
> with this?
> la $2, g1
>
> If that is the case, you can add this pattern.
>
> def op_la : Operand<i32>;
>
> def LA :
> FI<0x09, (outs CPURegs:$dst), (ins op_la:$addr0, op_la:$addr1),
> "la $dst, $addr0", [(set CPURegs:$dst,
> (add (MipsHi tglobaladdr:$addr0), (MipsLo
> tglobaladdr:$addr1)))], IIAlu>;
>
> Note that you still need to find a way to print "g1" instead of "%hi(g1)".
>
> On Wed, Oct...
2011 Oct 05
4
[LLVMdev] MIPS 32bit code generation
Hi,
In order to emit "la $4,ADDR" instead of lui followed by addiu to load
the data address, could you advise what is proper way to revise td files in
the MIPS target?
Thanks,
--
Gang-Ryung Uh, Associate Professor
Department of Computer Science
College of Engineering, Boise State Univerisity
tel: 1 208 426-5691 e-mail:guh at boisestate.edu
http://cs.boisestate.edu/~uh
2011 Oct 07
1
[LLVMdev] MIPS 32bit code generation
...gt; > addiu $2, $2, %lo(g1)
> >
> > with this?
> > la $2, g1
> >
> > If that is the case, you can add this pattern.
> >
> > def op_la : Operand<i32>;
> >
> > def LA :
> > FI<0x09, (outs CPURegs:$dst), (ins op_la:$addr0, op_la:$addr1),
> > "la $dst, $addr0", [(set CPURegs:$dst,
> > (add (MipsHi tglobaladdr:$addr0), (MipsLo
> > tglobaladdr:$addr1)))], IIAlu>;
> >
> > Note that you still need to find a way to print "g1" instead of
> "%hi(g1)&...
2016 Dec 07
3
[PATCH kernel v5 0/5] Extend virtio-balloon for fast (de)inflating & fast live migration
Removing silly virtio-dev@ list because it's bouncing mail...
On 12/07/2016 08:21 AM, David Hildenbrand wrote:
>> Li's current patches do that. Well, maybe not pfn/length, but they do
>> take a pfn and page-order, which fits perfectly with the kernel's
>> concept of high-order pages.
>
> So we can send length in powers of two. Still, I don't see any
2016 Dec 07
3
[PATCH kernel v5 0/5] Extend virtio-balloon for fast (de)inflating & fast live migration
Removing silly virtio-dev@ list because it's bouncing mail...
On 12/07/2016 08:21 AM, David Hildenbrand wrote:
>> Li's current patches do that. Well, maybe not pfn/length, but they do
>> take a pfn and page-order, which fits perfectly with the kernel's
>> concept of high-order pages.
>
> So we can send length in powers of two. Still, I don't see any
2016 Mar 15
3
the as-if rule / perf vs. security
...ad the extra memory,
> regardless of whether this is a masked load or something else.
>
> Note that the x86 backend already does this, so either my proposal is ok
> for x86, or we're already doing an illegal optimization:
>
>
> define <4 x i32> @load_bonus_bytes(i32* %addr1, <4 x i32> %v) {
> %ld1 = load i32, i32* %addr1
> %addr2 = getelementptr i32, i32* %addr1, i64 3
> %ld2 = load i32, i32* %addr2
> %vec1 = insertelement <4 x i32> undef, i32 %ld1, i32 0
> %vec2 = insertelement <4 x i32> %vec1, i32 %ld2, i32 3
> ret <...