search for: addpass

...; unable to find it. > > > > > > I have built a machine function pass similar to the one found in > > HexagonHardwareLoops.cpp. So I have generated a machine pass.cpp file, > > modified 'Target'.h and 'Target'TargetMachine.cpp (to add pass via > > addPass() in the addPreRegAlloc()). All this builds/compiles fine. > > > > > > When running llc the pass does not get executed. > > > > > > I seem to be missing some steps? Potentially registration of the > > machine pass? > > That should be all you need to d...

...better way? Possibly. What specifically do you object to? The main problem is that one needs different printers at different stages of the compiler: ModulePrinter, FunctionPrinter and MachineFunctionPrinter. It makes sense to write the code once and parameterize it on the printer type. I see addPass<> as the most "invasive" in the sense that the patch changes almost every call of PM.addPass(..) to addPass<>(PM, ...). That's a consequence of code sharing. I wanted a command-line interface that is intuitive. This requires that passes show up in the print option as a r...

Hi Danny, // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that // BasicAliasAnalysis wins if they disagree. This is intended to help // support "obvious" type-punning idioms. - if (UseCFLAA) - addPass(createCFLAliasAnalysisPass()); addPass(createTypeBasedAliasAnalysisPass()); addPass(createScopedNoAliasAAPass()); + if (UseCFLAA) + addPass(createCFLAliasAnalysisPass()); addPass(createBasicAliasAnalysisPass()); Do we really want to change the order here? I had originally placed it af...

Eli Friedman <eli.friedman at gmail.com> writes: >> Ah. So is the MachineFunction version expected to work correctly? > > It's part of the default set of CodeGen passes. It is? Was that true in 3.1? I can't see where it is initialized in llc. I probably missed something important. :) Thanks! -David

http://llvm.org/viewvc/llvm-project/llvm/tags/RELEASE_31/final/lib/CodeGen/Passes.cpp?revision=156747&view=markup void TargetPassConfig::addMachineSSAOptimization() { // Pre-ra tail duplication. if (addPass(EarlyTailDuplicateID) != &NoPassID) printAndVerify("After Pre-RegAlloc TailDuplicate"); /// Add passes that optimize machine instructions after register allocation. void TargetPassConfig::addMachineLateOptimization() { // Branch folding must be run after regalloc and prolog/ep...

...; hfinkel at anl.gov > > wrote: > > > Hi Danny, > > // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that > // BasicAliasAnalysis wins if they disagree. This is intended to help > // support "obvious" type-punning idioms. > - if (UseCFLAA) > - addPass( createCFLAliasAnalysisPass()); > addPass( createTypeBasedAliasAnalysisPa ss()); > addPass( createScopedNoAliasAAPass()); > + if (UseCFLAA) > + addPass( createCFLAliasAnalysisPass()); > addPass( createBasicAliasAnalysisPass() ); > > Do we really want to change the order here?...

Amara, first, thank you for answering. but I found expandPsuedo instructions actually happens before post-RA, like the following code showing: your approach is a little hacky, right? : ) // Expand pseudo instructions before second scheduling pass. addPass(&ExpandPostRAPseudosID); printAndVerify("After ExpandPostRAPseudos"); // Run pre-sched2 passes. if (addPreSched2()) printAndVerify("After PreSched2 passes"); // Second pass scheduler. if (getOptLevel() != CodeGenOpt::None) { addPass(&PostRASchedulerID...

...; Hi Danny, >> > >> > // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that >> > // BasicAliasAnalysis wins if they disagree. This is intended to help >> > // support "obvious" type-punning idioms. >> > - if (UseCFLAA) >> > - addPass( createCFLAliasAnalysisPass()); >> > addPass( createTypeBasedAliasAnalysisPa ss()); >> > addPass( createScopedNoAliasAAPass()); >> > + if (UseCFLAA) >> > + addPass( createCFLAliasAnalysisPass()); >> > addPass( createBasicAliasAnalysisPass() ); >> &...

...the documentation about registering a machine pass? I'm unable to find it. I have built a machine function pass similar to the one found in HexagonHardwareLoops.cpp. So I have generated a machine pass.cpp file, modified 'Target'.h and 'Target'TargetMachine.cpp (to add pass via addPass() in the addPreRegAlloc()). All this builds/compiles fine. When running llc the pass does not get executed. I seem to be missing some steps? Potentially registration of the machine pass? Thanks. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm...

...eatewawAnalyzer();" line to x86.h > 2. add file name to CMakelist.txt. > 3. This is going to run after postRAscheduler and before code emission so > I changed the x86TrgetMachine.cpp as follow: > void X86PassConfig::addPreEmitPass() { > /////////////add mypass here/////// > addPass(createwawAnalyzer()); > ////////////////////////////////// > if (getOptLevel() != CodeGenOpt::None) > addPass(createExecutionDependencyFixPass(&X86::VR128RegClass)); > > if (UseVZeroUpper) > addPass(createX86IssueVZeroUpperPass()); > > if (getOptLevel() !=...

...ode is emitted. If you're using the X86 target, then the class and the function is already there: lib/Target/X86/X86TargetMachine.cpp: bool X86PassConfig::addPreEmitPass() { bool ShouldPrint = false; if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) { addPass(createExecutionDependencyFixPass(&X86::VR128RegClass)); ShouldPrint = true; } if (getX86Subtarget().hasAVX() && UseVZeroUpper) { addPass(createX86IssueVZeroUpperPass()); ShouldPrint = true; } return ShouldPrint; } -Krzysztof -- Qualcomm Innovation Cente...

On Dec 14, 2011, at 7:09 AM, David Gardner wrote: > I'm attempting to add some support for hoisting/sinking of memory-using > intrinsics in loops, and so I want to use MemoryDependenceAnalysis in > LICM, but when I modify getAnalysisUsge to include this : > > virtual void getAnalysisUsage(AnalysisUsage &AU) const { > AU.setPreservesCFG(); >

On Mar 2, 2010, at 1:45 PM, David Greene wrote: > This set of patches adds support for dumping IR before or after specified > Passes. It adds the following command-line options: > > -print-before=<pass-option> > -print-after=<pass-option> > -print-before-all > -print-after-all This patch looks very invasive for such a simple thing, isn't there a better

...line to x86.h >> 2. add file name to CMakelist.txt. >> 3. This is going to run after postRAscheduler and before code emission so >> I changed the x86TrgetMachine.cpp as follow: >> void X86PassConfig::addPreEmitPass() { >> /////////////add mypass here/////// >> addPass(createwawAnalyzer()); >> ////////////////////////////////// >> if (getOptLevel() != CodeGenOpt::None) >> addPass(createExecutionDependencyFixPass(&X86::VR128RegClass)); >> >> if (UseVZeroUpper) >> addPass(createX86IssueVZeroUpperPass()); >>...

On Thu, Jan 15, 2015 at 1:26 PM, Nick Lewycky <nlewycky at google.com> wrote: > On 15 January 2015 at 13:10, Daniel Berlin <dberlin at dberlin.org> wrote: > >> Yes. >> I've attached an updated patch that does the following: >> >> 1. Fixes the partialalias of globals/arguments >> 2. Enables partialalias for cases where nothing has been unified to

...; wrote: > Amara, > > first, thank you for answering. but I found expandPsuedo instructions > actually happens before post-RA, like the following code showing: > your approach is a little hacky, right? : ) > > // Expand pseudo instructions before second scheduling pass. > addPass(&ExpandPostRAPseudosID); > printAndVerify("After ExpandPostRAPseudos"); > > // Run pre-sched2 passes. > if (addPreSched2()) > printAndVerify("After PreSched2 passes"); > > // Second pass scheduler. > if (getOptLevel() != CodeGenOpt::None...

...nonicalization passes to be run first, and composing both of them and promoting them into a single `FunctionPass` can reduce unnecessary runs of the canonicalization phases. With these, the pipeline can be built like: ``` FunctionPassManager FPM; LoopNestPassManager LNPM; LoopPassManager LPM; LNPM.addPass(SomeLoopNestPass()); LPM.addPass(SomeLoopPass()); LNPM.addPass(createLoopNestToLoopPassAdaptor(LPM)); FPM.addPass(createFunctionToLoopNestPassAdaptor(LNPM)); // This still works, but the loop canonicalization passes will be run twice: // FPM.addPass(createFunctionToLoopPassAdaptor(LPM)); // FPM.ad...

...> > > > // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that > > > // BasicAliasAnalysis wins if they disagree. This is intended to > > > help > > > // support "obvious" type-punning idioms. > > > - if (UseCFLAA) > > > - addPass( createCFLAliasAnalysisPass()); > > > addPass( createTypeBasedAliasAnalysisPa ss()); > > > addPass( createScopedNoAliasAAPass()); > > > + if (UseCFLAA) > > > + addPass( createCFLAliasAnalysisPass()); > > > addPass( createBasicAliasAnalysisPass() ); >...

I'm attempting to add some support for hoisting/sinking of memory-using intrinsics in loops, and so I want to use MemoryDependenceAnalysis in LICM, but when I modify getAnalysisUsge to include this : virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesCFG(); AU.addRequired<DominatorTree>(); AU.addRequired<LoopInfo>();

Thank you so much. That helped alot. Fami On Wed, Nov 4, 2015 at 9:40 AM, John Criswell <jtcriswel at gmail.com> wrote: > On 11/3/15 7:54 PM, fateme Hoseini wrote: > > Dear John, > Thank you so much for your help. I looked at those documents. Could you > kindly answer the following questions: > > Does it mean that I have to make my own backend target in order to write