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[LLVMdev] Question about porting LLVM - a single instruction op mnemonic with multiple operand forms
2011 Jan 18
4
[LLVMdev] Question about porting LLVM - a single instruction op mnemonic with multiple operand forms
...nemonic with multiple operand forms.
For example: Add R1, R2 & Add @R1, R2. I found that there is similar case in
x86 instruction set, such like ADD reg, reg & ADD mem, reg. However, the
solution of x86 is adding suffix of instruction and translating instruction
op mnemonic into ADDrr & ADDmr. I don't want to translate single instruction
op mnemonic with different operand forms into multiple op mnemonics. I am
wondering to know whether is another solution of this problem or not?? Which
target should I look for it??
thanks a lot
yi-hong
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An HT...
[LLVMdev] Question about porting LLVM - a single instruction op mnemonic with multiple operand forms
2011 Jan 18
0
[LLVMdev] Question about porting LLVM - a single instruction op mnemonic with multiple operand forms
...nemonic with multiple operand forms. For example: Add R1, R2 & Add @R1, R2. I found that there is similar case in x86 instruction set, such like ADD reg, reg & ADD mem, reg. However, the solution of x86 is adding suffix of instruction and translating instruction op mnemonic into ADDrr & ADDmr. I don't want to translate single instruction op mnemonic with different operand forms into multiple op mnemonics. I am wondering to know whether is another solution of this problem or not?? Which target should I look for it??
thanks a lot
yi-hong
-------------- next part --------------
An HT...
[LLVMdev] Question about porting LLVM - a single instruction op mnemonic with multiple operand forms
2011 Jan 18
1
[LLVMdev] Question about porting LLVM - a single instruction op mnemonic with multiple operand forms
...e operand forms.
> For example: Add R1, R2 & Add @R1, R2. I found that there is similar case in
> x86 instruction set, such like ADD reg, reg & ADD mem, reg. However, the
> solution of x86 is adding suffix of instruction and translating instruction
> op mnemonic into ADDrr & ADDmr. I don't want to translate single instruction
> op mnemonic with different operand forms into multiple op mnemonics. I am
> wondering to know whether is another solution of this problem or not?? Which
> target should I look for it??
>
>
>
> thanks a lot
>
>
>
>...
2009 Dec 08
2
[LLVMdev] Back-end with general purpose registers
Hi all,
I am trying to write a back-end for LLVM where any instruction may take
any type of data. I am looking for the output to be of the format:
inst.type reg1,reg2
etc. Where inst is the instruction, e.g. mov and type is data-type e.g.
f32 etc. I tried creating a back-end with a register class which could
take i32 and f32:
def GPRegs
: RegisterClass <"Test",