search for: addmbb

...uccessorsAndUpdatePHIs(BB); // Next, add the true and fallthrough blocks as its successors. BB->addSuccessor(copy0MBB); BB->addSuccessor(sinkMBB); // Emit the right instruction according to the type of the operands compared if (isFPCmp) BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); else BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg()) .addReg(Mips::ZERO).addMBB(sinkMBB); // copy0MBB: // %FalseValue = ... // # fallthrough to sinkMBB BB = copy0MBB; // Update machine-CFG edges BB->addSuccessor(sinkMBB);...

...ter(AddrRegClass); unsigned regC = MRI.createVirtualRegister(AddrRegClass); // Set the indice BuildMI(*MBB, MI, db, TII->get(X86::MOV64rr)).addReg(regA).addReg(X86::RSP); // Check condition BuildMI(*MBB_cond, MBB_cond->end(), db, TII->get(X86::PHI), regB).addReg(regA).addMBB(MBB).addReg(regC).addMBB(MBB_erase); BuildMI(*MBB_cond, MBB_cond->end(), db, TII->get(X86::CMP64rr)).addReg(regB).addReg(X86::RBP); BuildMI(*MBB_cond, MBB_cond->end(), db, TII->get(X86::JE_4)).addMBB(MBB_end); // mov dword[reg], 0x0 BuildMI(*MBB_erase, MBB_erase->end...

...); // Set the indice BuildMI(*MBB, MI, db, TII->get(X86::MOV64rr)).addReg(reg).addReg(X86::RSP); // Create the for loop condition BuildMI(*MBB_cond, MBB_cond->end(), db, TII->get(X86::CMP64rr)).addReg(reg).addReg(X86::RBP); BuildMI(*MBB_cond, MBB_cond->end(), db, TII->get(X86::JE_4)).addMBB(MBB_end); // Update phi node BuildMI(*MBB_erase, MBB_erase->end(), db, TII->get(X86::PHI), reg).addReg(reg).addMBB(MBB).addReg(reg).addMBB(MBB_erase); // Erase content of stack BuildMI(*MBB_erase, MBB_erase->end(), db, TII->get(X86::MOV32mi)) .addReg(reg).addImm(1).addReg(0).addImm(0).a...

This is the old MIPS I code that sort of does what I need to do. This seems really involved to do such a simple thing. Maybe there are now helper classes for this or some better example I can look at. I suppose I can mimick this if people say this just the correct way to do this in LLVM. static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,

...thisMBB = BB; - MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); - MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); - unsigned SelectPred = MI->getOperand(4).getImm(); - BuildMI(BB, TII->get(PPC::BCC)) - .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); - MachineFunction *F = BB->getParent(); - F->getBasicBlockList().insert(It, copy0MBB); - F->getBasicBlockList().insert(It, sinkMBB); - // Update machine-CFG edges by transferring all successors of the current - // block to the new block which will contain the Phi node for th...

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

...MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); - MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); - unsigned SelectPred = MI->getOperand(4).getImm(); - BuildMI(BB, TII->get(PPC::BCC)) - .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); - F->insert(It, copy0MBB); - F->insert(It, sinkMBB); - // Update machine-CFG edges by transferring all successors of the current - // block to the new block which will contain the Phi node for the select. - sinkMBB->transferSuccessors(BB); - // Next, add the true and fallth...

Hi Gary, This does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const

Evan Cheng wrote: > How about? > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > &PPC:G8RCRegClass; > unsigned TmpReg = RegInfo.createVirtualRegister(RC); I tried something like that yesterday: const TargetRegisterClass *RC = is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; but I kept getting this error no matter how I arranged it:

...he only option? In x86 assembly this would look something like: MOVQ 0x40044540, 0x8(%rsp) # Store address of trampoline basic block to stack The BuildMI looks like: BuildMI(MBB, MBIt, DL, TII->get(X86::MOV64mi32)) .addImm(0x1) // Scale .addReg(X86::RSP) // Base .addImm(0x8) // Disp .addMBB(my_target_mbb); // Source So far I have looked into the BuildMI API of LLVM and the only one that looks relevant is addMBB. While my LLVM pass compiles, my linker complains (and note that I am compiling with -fPIC): 1) /usr/bin/ld: /tmp/foo-d523b6.o: Unknown temporary symbol or 2) /usr/bin/ld...

You need to insert new basic blocks and update CFG to accomplish this. There is a hackish way to do this right now. Add a pseudo instruction to represent this operation and mark it usesCustomDAGSchedInserter. This means the intrinsic is mapped to a single (pseudo) node. But it is then expanded into instructions that can span multiple basic blocks. See

...thisMBB = BB; - MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); - MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); - unsigned SelectPred = MI->getOperand(4).getImm(); - BuildMI(BB, TII->get(PPC::BCC)) - .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); - MachineFunction *F = BB->getParent(); - F->getBasicBlockList().insert(It, copy0MBB); - F->getBasicBlockList().insert(It, sinkMBB); - // Update machine-CFG edges by transferring all successors of the current - // block to the new block which will contain the Phi node for th...

Would it be acceptable to change MachineInstr::getRegInfo from private to public so I can use it from PPCTargetLowering::EmitInstrWithCustomInserter? Cheers, Gary Evan Cheng wrote: > Look for createVirtualRegister. These are examples in > PPCISelLowering.cpp. > > Evan > On Jul 8, 2008, at 8:24 AM, Gary Benson wrote: > > > Hi Evan, > > > > Evan Cheng wrote:

Chris Lattner wrote: > On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: > > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: > > $label), > > "cmpw $rA, $rB\n\tbne- La${label}_exit", > > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: > > $label)]>; > > } > > > > ...and

...thisMBB = BB; - MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); - MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); - unsigned SelectPred = MI->getOperand(4).getImm(); - BuildMI(BB, TII->get(PPC::BCC)) - .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); - MachineFunction *F = BB->getParent(); - F->getBasicBlockList().insert(It, copy0MBB); - F->getBasicBlockList().insert(It, sinkMBB); - // Update machine-CFG edges by transferring all successors of the current - // block to the new block which will contain the Phi node for th...

...ddrRegClass); >> >> // Set the indice >> BuildMI(*MBB, MI, db, >> TII->get(X86::MOV64rr)).addReg(regA).addReg(X86::RSP); >> >> // Check condition >> BuildMI(*MBB_cond, MBB_cond->end(), db, TII->get(X86::PHI), >> regB).addReg(regA).addMBB(MBB).addReg(regC).addMBB(MBB_erase); >> BuildMI(*MBB_cond, MBB_cond->end(), db, >> TII->get(X86::CMP64rr)).addReg(regB).addReg(X86::RBP); >> BuildMI(*MBB_cond, MBB_cond->end(), db, >> TII->get(X86::JE_4)).addMBB(MBB_end); >> >> // mov dword[r...

...Is(MBB); + + MachineInstrBuilder MIB; + + unsigned LabelReg = MRI.createVirtualRegister(&SP::IntRegsRegClass); + unsigned BufReg = MI->getOperand(1).getReg(); + + MIB = BuildMI(*thisMBB, MI, DL, TII->get(SP::SETHIi)) + .addReg(LabelReg, RegState::Define) + .addMBB(sinkMBB, SparcMCExpr::VK_Sparc_HI); + MIB.setMemRefs(MMOBegin, MMOEnd); + + MIB = BuildMI(*thisMBB, MI, DL, TII->get(SP::ADDri)) + .addReg(LabelReg) + .addReg(LabelReg) + .addMBB(sinkMBB, SparcMCExpr::VK_Sparc_LO); + MIB.setMemRefs(MMOBegin, MMOEnd); + +...

After discussions last night, I'm leaning towards going legit with all my pseudo expansions in Mips 16. Some I think I can clearly do by just putting in the proper side effects of implicit registers (T8 the condition code register as used by mips 16). But I'm still left with some pseudos that have jmp .+4 type instructions in them. The original Mips port was to Mips I and Mips I,

....5740b49 100644 > --- a/lib/Target/BPF/BPFISelLowering.cpp > +++ b/lib/Target/BPF/BPFISelLowering.cpp > @@ -578,11 +578,15 @@ > BPFTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, > .addReg(LHS) > .addReg(MI.getOperand(2).getReg()) > .addMBB(Copy1MBB); > - else > + else { > + int64_t imm32 = MI.getOperand(2).getImm(); > + // sanity check before we build J*_ri instruction. > + assert (isInt<32>(imm32)); > BuildMI(BB, DL, TII.get(NewCC)) > .addReg(LHS) > - .addImm(MI.getOperan...