Displaying 3 results from an estimated 3 matches for "addico".
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addicon
2013 Apr 12
2
[LLVMdev] TableGen list merging
Hi,
In the PPC backend, there is a "helper" class used to define instructions that implicitly define a condition register:
class isDOT {
list<Register> Defs = [CR0];
bit RC = 1;
}
and this gets used on instructions such as:
def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
"addic. $rD, $rA, $imm", IntGeneral,
[]>, isDOT;
but there is a small problem. If these instructions are also part of a larger block which also defines registers, like this:
let D...
2013 Apr 12
0
[LLVMdev] TableGen list merging
...> In the PPC backend, there is a "helper" class used to define instructions that implicitly define a condition register:
>
> class isDOT {
> list<Register> Defs = [CR0];
> bit RC = 1;
> }
>
> and this gets used on instructions such as:
>
> def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
> "addic. $rD, $rA, $imm", IntGeneral,
> []>, isDOT;
>
> but there is a small problem. If these instructions are also part of a larger block which also defines registers,...
2013 Apr 12
1
[LLVMdev] TableGen list merging
...; class used to define
> > instructions that implicitly define a condition register:
> >
> > class isDOT {
> > list<Register> Defs = [CR0];
> > bit RC = 1;
> > }
> >
> > and this gets used on instructions such as:
> >
> > def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA,
> > s16imm:$imm),
> > "addic. $rD, $rA, $imm", IntGeneral,
> > []>, isDOT;
> >
> > but there is a small problem. If these instructions are also part
> > of a la...