search for: addgg

Displaying 4 results from an estimated 4 matches for "addgg".

Did you mean: addgl
2005 Jul 25
2
[LLVMdev] How to partition registers into different RegisterClass?
...partition the register into different RegisterClass: input, output, general purpose, constant, etc. def GeneralPurposeRC : RegisterClass<packed, 128, [R0, R1]>; def InputRC : RegisterClass<packed, 128, [V0, V1]>; def ConstantRC : RegisterClass<packed, 128, [C0, C1]>; def ADDgg : BinaryInst<0x51, ( ops GeneralPurposeRC :$dest, ope GeneralPurposeRC :$src), "add $dest, $src">; def ADDgi : BinaryInst<0x52, ( ops GeneralPurposeRC :$dest, ope InputRC :$src), "add $dest, $src">; def ADDgc : BinaryInst<0x52, ( ops GeneralPurp...
2005 Jul 23
0
[LLVMdev] How to partition registers into different RegisterClass?
On Sat, 23 Jul 2005, Tzu-Chien Chiu wrote: > 2005/7/23, Chris Lattner <sabre at nondot.org>: >> What does a 'read only' register mean? Is it a constant (e.g. returns >> 1.0)? Otherwise, how can it be a useful value? > > Yes, it's a constant register. > > Because the instruction cannot contain an immediate value, a constant > value may be stored in
2005 Jul 23
3
[LLVMdev] How to partition registers into different RegisterClass?
2005/7/23, Chris Lattner <sabre at nondot.org>: > > What does a 'read only' register mean? Is it a constant (e.g. returns > 1.0)? Otherwise, how can it be a useful value? Yes, it's a constant register. Because the instruction cannot contain an immediate value, a constant value may be stored in a constant register, and it's defined _before_ the program starts by
2005 Jul 26
0
[LLVMdev] How to partition registers into different RegisterClass?
...s, there should be a single register class. If there are two adds (as it looks like you have below, judging by the opcode) with different register constraints, then you should partition the registers so that each the register classes line up with the instruction operand requirements. > def ADDgg : BinaryInst<0x51, ( > ops GeneralPurposeRC :$dest, > ope GeneralPurposeRC :$src), "add $dest, $src">; > > def ADDgi : BinaryInst<0x52, ( > ops GeneralPurposeRC :$dest, > ope InputRC :$src), "add $dest, $src">; > > def ADDgc : BinaryIn...