search for: addedcomplex

Displaying 20 results from an estimated 47 matches for "addedcomplex".

2009 Apr 06
2
[LLVMdev] ISel Pattern Preferences
...wide variety of store instructions. Pattern B has a narrower predicate meant to catch very specific store instructions that would also satisfy the predicate for Pattern A. We used to match Pattern B just fine but after changing .td files a bit the selector is always picking Pattern A. Setting AddedComplexity doesn't seem to help. -Dave
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...uot;memd(#$global+$offset) = $src", >> []>; >> @@ -1758,30 +1758,30 @@ def POST_STdri : STInstPI<(outs IntRegs:$dst), >> // Store doubleword conditionally. >> // if ([!]Pv) memd(Rs+#u6:3)=Rtt >> // if (Pv) memd(Rs+#u6:3)=Rtt >> -let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in >> -def STrid_cPt : STInst<(outs), >> +let AddedComplexity = 10, neverHasSideEffects = 1 in >> +def STrid_cPt : STInst2<(outs), >> (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2), >>...
2009 Apr 06
0
[LLVMdev] ISel Pattern Preferences
...ions. Pattern B has a narrower > predicate meant to catch very specific store instructions that would also > satisfy the predicate for Pattern A. > > We used to match Pattern B just fine but after changing .td files a bit the > selector is always picking Pattern A. > > Setting AddedComplexity doesn't seem to help. Urk. I set AddedComplexity on the wrong thing. Seems to work now. -Dave
2009 Apr 07
2
[LLVMdev] ISel Pattern Preferences
David, Would you mind documenting what you did with AddedComplexity for the 'less fortunate' on the wiki? Thanks, Justin. On Mon, Apr 6, 2009 at 9:47 PM, David Greene <dag at cray.com> wrote: > On Monday 06 April 2009 13:31, David Greene wrote: > > What's a reliable way to prefer one patterns over another? I have two > > patt...
2013 Feb 12
1
[LLVMdev] pattern matching order
...at mips.com> wrote: > >> It seems that patterns are matched in the order that they appear in the td file. >> Is this something we can rely on? > > It is by design but it is the last resort for ordering, and it is very fragile to depend on that. > > It is better to use AddedComplexity to control pattern ordering when required. This matches my experience. BTW, why is it called "AddedComplexity?" That's a quite misleading name. Should we rename it to something else, maybe, "SelectionWeight?" "SelectionPriority" would be better still but tha...
2013 Feb 08
2
[LLVMdev] pattern matching order
It seems that patterns are matched in the order that they appear in the td file. Is this something we can rely on? def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>; def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>; the immSExt8 will only match a 8 bit signed value. I want it to try the first pattern and then the second, if it fails. AddiuRxRxImm16 --- 16 bit
2013 Feb 08
0
[LLVMdev] pattern matching order
...Reed Kotler <rkotler at mips.com> wrote: > It seems that patterns are matched in the order that they appear in the td file. > > Is this something we can rely on? It is by design but it is the last resort for ordering, and it is very fragile to depend on that. It is better to use AddedComplexity to control pattern ordering when required. /jakob
2008 Oct 07
2
[LLVMdev] Making Sense of ISel DAG Output
...es, but nodes can also become dead > during selection. Some parts of selection know how to clean up > nodes that become dead during selection, but my guess is that > it's missing some cases. Ok, as far as I can tell, here's what's happening. I have the following pattern: let AddedComplexity = 40 in { def : Pat<(v2f64 (vector_shuffle (v2f64 (scalar_to_vector (loadf64 addr: $src1))), (v2f64 (scalar_to_vector (loadf64 addr: $src2))), SHUFP_shuffle_mask:$sm)), (SHUFPDrri (v2f64 (MOVSD2PDrm addr:$src...
2013 May 16
1
[LLVMdev] Undoing DAG Combiner patterns
A better way to handle this is to a td pattern to match "add n, -c" to a subtraction. I believe several targets do something similar to this. Evan On May 16, 2013, at 7:12 AM, Tom Stellard <tom at stellard.net> wrote: > On Thu, May 16, 2013 at 02:03:14AM +0000, Martin Filteau wrote: >> Hi all, >> >> It's the first LLVM backend we do for our asynchronous
2016 Jun 28
2
Question about Instruction Selection
...ogramming >> selection, it still needs a cost model to help it making decisions. So where >> is it? > > There is a cost of sorts used to generate the matchers: it's usually > the size (complexity) of the pattern to match. Patterns can then > override it using the "AddedComplexity" field. > > There is also a cost model for the output patterns, based on the > number of selected instructions and estimates of their encoded sizes. > It's used as a tie-breaker when the input complexity is equal. > Sorry that I didn’t state the question clear: “cost”...
2016 Jun 28
0
Question about Instruction Selection
...c programming > selection, it still needs a cost model to help it making decisions. So where > is it? > > > There is a cost of sorts used to generate the matchers: it's usually > the size (complexity) of the pattern to match. Patterns can then > override it using the "AddedComplexity" field. > > There is also a cost model for the output patterns, based on the > number of selected instructions and estimates of their encoded sizes. > It's used as a tie-breaker when the input complexity is equal. > > > Sorry that I didn’t state the question clear:...
2008 Sep 24
0
[LLVMdev] Multi-Instruction Patterns
...m, but how > do I tell the selection DAG to prefer my pattern over another that > already exists. I can't easily just disable that other pattern > because > it generates Machine Instruction opcode enums that are assumed to be > available in other parts of the x86 codegen. Try AddedComplexity = n to increase "goodness" of the pattern. It's a bit of a hack. > > > So given two patterns that match the same thing, what's the > tiebreaker? > I thought it was order in the .td file but that doesn't appear to be > the > case. I put my patter...
2009 Apr 07
0
[LLVMdev] ISel Pattern Preferences
On Tuesday 07 April 2009 01:20, someguy wrote: > David, > Would you mind documenting what you did with AddedComplexity for the 'less > fortunate' on the wiki? Yep. Will do. Hmm...is there a link to the Wiki on the main page? I can't find it. -Dave
2010 Jan 04
1
[LLVMdev] Assembly Printer
...way to do this kind of thing. It eventually leads to confusion where someone things SRA means "sra" and someone else thinks it meas "mysra." It gets worse as "mysra" acquires subtly different semantics than "sra." Better to write a separate pattern and use AddedComplexity to prefer it. Just a nugget of wisdom from personal experience. :) -Dave
2008 Sep 24
2
[LLVMdev] Multi-Instruction Patterns
Chris Lattner wrote: > On Sep 23, 2008, at 11:26 AM, David Greene wrote: > >> Are there any examples of using tablegen to generate multiple machine >> instructions from a single pattern? Or do these cases always have >> to be >> manually expanded? > > PPC has a bunch of examples, for example: > > // Arbitrary immediate support. Implement in terms of
2008 Oct 02
0
[LLVMdev] Making Sense of ISel DAG Output
On Thursday 02 October 2008 11:37, David Greene wrote: > I'll try ot write a small example and send it in a bit. Ok, here's what I'm trying to do: let AddedComplexity = 40 in { def : Pat<(v2f64 (vector_shuffle (v2f64 (scalar_to_vector (loadf64 addr: $src1))), (v2f64 (scalar_to_vector (loadf64 addr: $src2))), SHUFP_shuffle_mask:$sm)), (SHUFPDrri (v2f64 (MOVSD2PDrm addr:$src1)),...
2008 Oct 07
0
[LLVMdev] Making Sense of ISel DAG Output
...> during selection. Some parts of selection know how to clean up >> nodes that become dead during selection, but my guess is that >> it's missing some cases. > > Ok, as far as I can tell, here's what's happening. > > I have the following pattern: > > let AddedComplexity = 40 in { > def : Pat<(v2f64 (vector_shuffle (v2f64 (scalar_to_vector (loadf64 > addr: > $src1))), > (v2f64 (scalar_to_vector (loadf64 > addr: > $src2))), > SHUFP_shuffle_mask:$sm)), >...
2008 Oct 20
2
[LLVMdev] TableGen Hacking Help
Ok, this is really complicated. I need some TableGen experts to help here. I need a little help doing a final bit of tblgen hacking. I've hacked tblgen to handle patterns like this: let AddedComplexity = 40 in { def : Pat<(vector_shuffle (v2f64 (scalar_to_vector (loadf64 addr:$src1))), (v2f64 (scalar_to_vector (loadf64 addr:$src2))), SHUFP_shuffle_mask:$sm), (SHUFPDrri (MOVSD2PDrm addr:$src1), (MOVSD2PDrm...
2008 Oct 03
0
[LLVMdev] Making Sense of ISel DAG Output
On Fri, October 3, 2008 9:10 am, David Greene wrote: > On Thursday 02 October 2008 19:32, Dan Gohman wrote: > >> Looking at your dump() output above, it looks like the pre-selection >> loads have multiple uses, so even though you've managed to match a >> larger pattern that incorporates them, they still need to exist to >> satisfy some other users. > > Yes,
2008 Oct 03
3
[LLVMdev] Making Sense of ISel DAG Output
On Thursday 02 October 2008 19:32, Dan Gohman wrote: > Looking at your dump() output above, it looks like the pre-selection > loads have multiple uses, so even though you've managed to match a > larger pattern that incorporates them, they still need to exist to > satisfy some other users. Yes, I looked at that too. It looks like these other uses end up being chains to