Displaying 3 results from an estimated 3 matches for "adddefaultpr".
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adddefaultpred
2014 Aug 20
2
[LLVMdev] ARMv4T Copy Lowering
...) const {
return 0;
}
void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const {
- AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
- .addReg(SrcReg, getKillRegState(KillSrc)));
+ // Need to check the arch.
+ MachineFunction &MF = *MBB.getParent();
+ const ARMSubtarget &st = MF.getTarget().getSubtarget<ARMSubtarget>();
+
assert(ARM::GPRRegClass.contains(Dest...
2015 Jan 11
3
[LLVMdev] [RFC] [PATCH] add tail call optimization to thumb1-only targets
...- 1;
+ assert (StackSlotForSavedLR >= 0 && "Wrong Stack slot for LR.");
+
+ // Make sure that R4 may be used as scratch. Add an additional tPUSH (R4)
+ // if necessary.
+ if (!IsR4IncludedInCSI) {
+ IsR4ToBeAdditionallyAddedToPopIns = true;
+
+ AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPUSH))
+ .addReg(ARM::R4,RegState::Kill));
+
+ StackSlotForSavedLR ++;
+ }
+
+ AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRspi))
+ .addReg(ARM::R4, RegState::Define)
+ .addReg(ARM::SP)
+ .addImm(Stack...
2013 Feb 20
1
[LLVMdev] Question about accessing coprocesser register in prologue
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