search for: adda_32_dx

...terns can't take into account register classes. The > register classes in the patterns are a selection constraint for the register > allocator if that instruction is chosen, not a constraint on choosing that > pattern. > > Here's a possible way to proceed for now: > Define ADDA_32_dx without a pattern. Then in C++ pattern code for matching > address operands select add operations on addresses to ADDA_32_dx. This way > you know that the add your selecting is going to be used as an address and > you can safely tell the register allocator to put the value in an address &g...

...d effect. AR is the address register class, DR32 is the data register class (no overlap): // 32-bit add DR->DR def ADD_32_dx_dx : I<(outs DR32:$dst), (ins DR32:$src1, DR32:$src2), "add.l $src2, $dst", [(set DR32:$dst, (add DR32:$src2, DR32:$src1))]>; // 32-bit add DR->AR def ADDA_32_dx : I<(outs AR:$dst), (ins AR:$src1, DR32:$src2), "adda.l $src2, $dst", [(set AR:$dst, (add AR:$src1, DR32:$src2))]>; Tablegen tells me that "Pattern '(add:i32 DR32:i32:$src2, DR32:i32:$src1)' is impossible to select", but I can't figure out why. Are register cl...

...lass, DR32 is the > data register class (no overlap): > > // 32-bit add DR->DR > def ADD_32_dx_dx : I<(outs DR32:$dst), (ins DR32:$src1, DR32:$src2), > "add.l $src2, $dst", [(set DR32:$dst, (add DR32:$src2, DR32:$src1))]>; > > // 32-bit add DR->AR > def ADDA_32_dx : I<(outs AR:$dst), (ins AR:$src1, DR32:$src2), "adda.l > $src2, $dst", [(set AR:$dst, (add AR:$src1, DR32:$src2))]>; > > Tablegen tells me that "Pattern '(add:i32 DR32:i32:$src2, > DR32:i32:$src1)' is impossible to select", but I can't figure out w...

...sses. The >> register classes in the patterns are a selection constraint for >> the register >> allocator if that instruction is chosen, not a constraint on >> choosing that >> pattern. >> >> Here's a possible way to proceed for now: >> Define ADDA_32_dx without a pattern. Then in C++ pattern code for >> matching >> address operands select add operations on addresses to ADDA_32_dx. >> This way >> you know that the add your selecting is going to be used as an >> address and >> you can safely tell the registe...

...classes in the patterns are a selection constraint for >>> the register >>> allocator if that instruction is chosen, not a constraint on >>> choosing that >>> pattern. >>> >>> Here's a possible way to proceed for now: >>> Define ADDA_32_dx without a pattern. Then in C++ pattern code for >>> matching >>> address operands select add operations on addresses to ADDA_32_dx. >>> This way >>> you know that the add your selecting is going to be used as an >>> address and >>> you can...

...CSE, etc. Scheduling and register allocation happen later. Let me clarify. Write "generic" instructions, i.e. those that use / def DR32, with patterns. So right after isel, all the DAG nodes will be of the dx variant, e.g. ADD_32_dx_dx. Also write AR instruction variants such as ADDA_32_dx. These do not have patterns so they aren't used during selection. Add a post pass to replace load / store operands by replacing them with identical nodes except for the "correct" opcodes. I think this mechanism will work. There is probably a cleaner solution. But I am not see...

...uling and register allocation happen later. > > Let me clarify. Write "generic" instructions, i.e. those that use / > def DR32, with patterns. So right after isel, all the DAG nodes will > be of the dx variant, e.g. ADD_32_dx_dx. Also write AR instruction > variants such as ADDA_32_dx. These do not have patterns so they > aren't used during selection. Add a post pass to replace load / store > operands by replacing them with identical nodes except for the > "correct" opcodes. > > I think this mechanism will work. There is probably a cleaner > solut...

On 9/24/07, Evan Cheng <evan.cheng at apple.com> wrote: > I am going to suggest something shocking. :) Since you will end up writing a > bunch of target specific code anyway, you might a well write a target > specific pass that change generic instructions into data register variant > ones when necessary. Hi Evan, wouldn't this generate fairly terrible code if each address

...llocation happen later. >> >> Let me clarify. Write "generic" instructions, i.e. those that use / >> def DR32, with patterns. So right after isel, all the DAG nodes will >> be of the dx variant, e.g. ADD_32_dx_dx. Also write AR instruction >> variants such as ADDA_32_dx. These do not have patterns so they >> aren't used during selection. Add a post pass to replace load / store >> operands by replacing them with identical nodes except for the >> "correct" opcodes. >> >> I think this mechanism will work. There is probably...