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add_type1
2018 Dec 07
3
Implement VLIW Backend on LLVM (Assembler Related Questions)
...ser see "add Ri, Rj, Rk", it generates one encoding, but when
parser see another "add Ri, Rj, Rk", it will modify previously generated
encoding.
I would like to know can LLVM's assembler support this?
Or I should define my instruction in this way:
add_type1 Ri, Rj, Rk
add_type2 Ri, Rj, Rk, Rl, Rm, Rn
add_type3 Ri, Rj, Rk, Rl, Rm, Rn, Ro, Rp, Rq
Q2.
Some of the instructions need to setup additional configuration, e.g.
{
scache wa ; Set cache mode: write allocate
ssize 64 ; Set write size = 64 bits
sendian big ; Set big endian writing
store R0, 0x10...