Displaying 2 results from an estimated 2 matches for "add_reg_imm".
2011 Nov 03
3
[LLVMdev] Tablegen: Instructions that take immediates or registers as operands
...r
32-bit floating point immediates as arguments. I was wondering if there
is a way to model this using tablegen, without having to define an
instruction for each possible combination of registers and immediates
(e.g. For ADD it would require four definitions: ADD_imm_imm,
ADD_reg_reg, ADD_imm_reg, ADD_reg_imm).
I have tried a few different ways to make this work in tablegen, but I
have been unsuccessful so far. Here is an example of something I have
tried. It fails to compile with tablegen, but I hope it can help
demonstrate what I am trying to do:
def F32Node : PatLeaf<(vt), [{return N->getV...
2011 Nov 03
0
[LLVMdev] Tablegen: Instructions that take immediates or registers as operands
...mmediates as arguments. I was wondering if
> there
> is a way to model this using tablegen, without having to define an
> instruction for each possible combination of registers and immediates
> (e.g. For ADD it would require four definitions: ADD_imm_imm,
> ADD_reg_reg, ADD_imm_reg, ADD_reg_imm).
>
> I have tried a few different ways to make this work in tablegen, but I
> have been unsuccessful so far. Here is an example of something I have
> tried. It fails to compile with tablegen, but I hope it can help
> demonstrate what I am trying to do:
>
>
> def F32Nod...