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This adds support for vhost-net virtio kernel backend. This is not intented for merge. See vhost net patch description for details. This applies on top of commit 47e465f031fc43c53ea8f08fa55cc3482c6435c8 in Avi's tree. It won't apply to tree tip. TODO: rebase. The patchset also includes raw socket backend since I find it useful for testing vhost. When we get to merging, there's no

This adds support for vhost-net virtio kernel backend. This is not intented for merge. See vhost net patch description for details. This applies on top of commit 47e465f031fc43c53ea8f08fa55cc3482c6435c8 in Avi's tree. It won't apply to tree tip. TODO: rebase. The patchset also includes raw socket backend since I find it useful for testing vhost. When we get to merging, there's no

Hello. I come back to this older thread. Again, because of i64immSExt32 I receive TableGen error "Could not infer all types in, pattern!" (exact details written below). So far I'm not able to generate selection code with TableGen for the ADD_r* instructions, etc: def i64immSExt32 : PatLeaf<(imm), [{return isInt<32>(N->getSExtValue()); }]>; As in the case of https://groups.google.com/forum/#!topic/llvm-dev/LfltBGG9ru0 : "It seems that defining a new register class changes how the tbl...

Hello. I've tried to add some simple arithmetic vector operations to the BPF backend available in the LLVM repo. Because I added in BPFRegisterInfo.td another RegisterClass (taken from the Mips backend): def MSA128W: RegisterClass<"BPF", [v2i64, v2f64], 128, (sequence "W%u", 0, 31)>; in order to support vector for example, ADD