search for: add_int

...check-prefix=FUNC %s > +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG --check-prefix=FUNC %s > +; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s > > ;FUNC-LABEL: @test1: > -;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} > +;EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} > > -;SI-CHECK: V_ADD_I32_e32 [[REG:v[0-9]+]], {{v[0-9]+, v[0-9]+}} > -;SI-CHECK-NOT: [[REG]] > -;SI-CHECK: BUFFER_STORE_DWORD [[REG]], >...

...MP0x, TEMP0x, 0 LOADgis TEMP1z, [TEMP1y] UADDs TEMP1y, TEMP1y, 4 LOADgis TEMP1y, [TEMP1y] UADDs TEMP1y, TEMP1z, TEMP1y STOREgis [TEMP1x], TEMP1y UADDs TEMP0x, TEMP0x, 0 RET ENDSUB and add.ll has: ;FUNC-LABEL: {{^}}test1: ;EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;SI: v_add_i32_e32 [[REG:v[0-9]+]], vcc, {{v[0-9]+, v[0-9]+}} ;SI-NOT: [[REG]] ;SI: buffer_store_dword [[REG]], define void @test1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i...

...; = COPY %vreg37<kill>; R600_Reg128:%vreg10 R600_Reg32:%vreg37 1056B%vreg9<def> = COPY %vreg6:sel_z<kill>; R600_Reg32:%vreg9 R600_Reg128:%vreg6 1072B%vreg38<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 1; R600_Reg32:%vreg38 1088B%vreg11<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0, 0, 0, %vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg11,%vreg7,%vreg38 1104B%vreg47<def> = COPY %vreg9<kill>; R600_Reg32:%vreg47,%vreg9 1120B%vreg48<def> = COPY %vreg10<kill>; R600_Reg128:%vreg48,%vreg10 1136B...

...7<kill>; R600_Reg128:%vreg10 R600_Reg32:%vreg37 > 1056B%vreg9<def> = COPY %vreg6:sel_z<kill>; R600_Reg32:%vreg9 R600_Reg128:%vreg6 > 1072B%vreg38<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 1; R600_Reg32:%vreg38 > 1088B%vreg11<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0, 0, 0, %vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg11,%vreg7,%vreg38 > 1104B%vreg47<def> = COPY %vreg9<kill>; R600_Reg32:%vreg47,%vreg9 > 1120B%vreg48<def> = COPY %vreg10<kill>; R600_Reg128:%vreg48,%vr...

Hi All, So as discussed I've started working on a TGSI backend for llvm to use as a way to get compute going on nouveau (and other gpu-s). I'm still learning all the ins and outs of llvm so I do not have much to show yet. I've rebased Francisco's (curro's) latest version on top of llvm trunk, and added a commit on top to actual get it build with the latest trunk. So

In the creation of dynamic languages we often have to box values together. For instance, take the following expression: IntObj c = sqrt((a*a)+(b*b)); Here, most likely, a bytecode interpreter would execute this as "mul_ints", "add_ints", "sqrt", etc. Inside these primitive functions we would have to unwrap our IntObj types, add the values, allocate a new object and return that to the function. In the above example, we could probably expect around 4 allocations, and 7 unboxing operations. Now granted if my lanugage...

...:%vreg10,%vreg32 %vreg10:sel_z<def> = COPY %vreg47; R600_Reg128:%vreg10 R600_Reg32:%vreg47 %vreg10:sel_w<def> = COPY %vreg32:sel_w; R600_Reg128:%vreg10,%vreg32 %vreg38<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 1; R600_Reg32:%vreg38 %vreg11<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg49, 0, 0, 0, %vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg11,%vreg49,%vreg38 %vreg47<def> = COPY %vreg32:sel_z; R600_Reg32:%vreg47 R600_Reg128:%vreg32 %vreg32<def> = COPY %vreg10; R600_Reg128:%vreg32,%vreg10 %vreg49<def> = COPY %vr...

Hi Vincent, On 25/10/2012 18:14, Vincent Lejeune wrote: > When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg. > > If I look at the : > %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6 > > instructions ; it gets joined to : > 928B%vreg34<def> = COPY %vreg48:sel_y; > > when vreg6 and

...; %vreg10:sel_z<def> = COPY %vreg47; R600_Reg128:%vreg10 R600_Reg32:%vreg47 > %vreg10:sel_w<def> = COPY %vreg32:sel_w; R600_Reg128:%vreg10,%vreg32 > %vreg38<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 1; R600_Reg32:%vreg38 > %vreg11<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg49, 0, 0, 0, %vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg11,%vreg49,%vreg38 > %vreg47<def> = COPY %vreg32:sel_z; R600_Reg32:%vreg47 R600_Reg128:%vreg32 > %vreg32<def> = COPY %vreg10; R600_Reg128:%vreg32,%vreg10 > %vreg49<def...

...USA. + *) + +(* Test the Getopt module. The tests are controlled by the + * test-getopt.sh script. + *) + +open Printf + +open Common_utils +open Getopt.OptionName + +let adds = ref [] +let add_string = push_back adds + +let anons = ref [] +let anon_fun = push_back anons + +let ints = ref [] +let add_int = push_back ints + +let clear_flag = ref true +let set_flag = ref false +let si = ref 42 +let ss = ref "not set" + +let argspec = [ + [ S 'a'; L"add" ], Getopt.String ("string", add_string), "Add string"; + [ S 'c'; L"clear" ], Ge...

...1056B%vreg9<def> = COPY %vreg6:sel_z<kill>; R600_Reg32:%vreg9 R600_Reg128:%vreg6 register: %vreg9 +[1056r,1104r:0) 1072B%vreg38<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 1; R600_Reg32:%vreg38 register: %vreg38 +[1072r,1088r:0) 1088B%vreg11<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0, 0, 0, %vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg11,%vreg7,%vreg38 register: %vreg11 +[1088r,1136r:0) 1104B%vreg47<def> = COPY %vreg9<kill>; R600_Reg32:%vreg47,%vreg9 register: %vreg47 phi-join +[1104r,1168B:2) 1120B%...

...reg6:sel_z<kill>; R600_Reg32:%vreg9 > R600_Reg128:%vreg6 > register: %vreg9 +[1056r,1104r:0) > 1072B%vreg38<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, > pred:%PRED_SEL_OFF, 1; R600_Reg32:%vreg38 > register: %vreg38 +[1072r,1088r:0) > 1088B%vreg11<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0, 0, 0, > %vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; > R600_Reg32:%vreg11,%vreg7,%vreg38 > register: %vreg11 +[1088r,1136r:0) > 1104B%vreg47<def> = COPY %vreg9<kill>; R600_Reg32:%vreg47,%vreg9 > register: %vreg47 phi-j...

...quest({ method = "PUT", url = ctx.ep, source = ltn12.source.string(reqbody), headers={ ["content-type"] = "application/json; charset=utf-8", ["content-length"] = tostring(#reqbody) } }) e:add_int("result_code", code) e:log_info("Mail notify status " .. tostring(code)) end end This leads to a couple more questions ;) - is there a way (eg. return value) to stop event processing already in dovecot_lua_notify_begin_txn - sometimes multiple events are generated, e...

...ays_log_source>, add_categories = 0x7f29785bfb00 <event_passthrough_add_categories>, add_category = 0x7f29785bfb70 <event_passthrough_add_category>, add_fields = 0x7f29785bfe80 <event_passthrough_add_fields>, add_str = 0x7f29785bfcc0 <event_passthrough_add_str>, add_int = 0x7f29785bfd40 <event_passthrough_add_int>, add_timeval = 0x7f29785bfdd0 <event_passthrough_add_timeval>, event = 0x7f29785bedd0 <event_passthrough_event>}, prev = 0x55ac2dac51a0, next = 0x55ac2da75be0, refcount = 0, pool = 0x55ac2dab8070, parent = 0x0, id = 2, log_prefix =...

The second patch is obviously not complete yet - for discussion only. Rich.

Thanks Aki, I'll check it out :) Am 03.08.20 um 11:40 schrieb Aki Tuomi: >> On 03/08/2020 12:31 Ralf Becker <rb at egroupware.org> wrote: >> >> >> We're currently using the OX push driver, which is straight forward >> (simple web hook) and allows to store (multiple) push tokens of our >> webmailer direct in mailbox metadata. >> >>

v1 -> v2: - Further fixes to Getopt int parsing. - Completed the L/S changes. - Fixed the test suite so it passes now. Also we don't need the special-case tests for 64 bit arch. Rich.

v3 -> v4: - Pushed the first patch upstream since it was ACKed. - Prevent use of M except for the special virt-v2v options. - Sort the options after added --help etc. - Make corresponding fixes to the tests. Rich.

v2 -> v3: - Add M variant and test it. Rich.

v2 -> v3: - Renamed List.assoc_ -> List.assoc_lbl. - Rebased on top of current master branch. Rich.