Displaying 11 results from an estimated 11 matches for "add_atomic_switch_msr".
2017 Sep 25
2
[PATCH v1 4/4] KVM/vmx: enable lbr for the guest
> +static void auto_switch_lbr_msrs(struct vcpu_vmx *vmx)
> +{
> + int i;
> + struct perf_lbr_stack lbr_stack;
> +
> + perf_get_lbr_stack(&lbr_stack);
> +
> + add_atomic_switch_msr(vmx, MSR_LBR_SELECT, 0, 0);
> + add_atomic_switch_msr(vmx, lbr_stack.lbr_tos, 0, 0);
> +
> + for (i = 0; i < lbr_stack.lbr_nr; i++) {
> + add_atomic_switch_msr(vmx, lbr_stack.lbr_from + i, 0, 0);
> + add_atomic_switch_msr(vmx, lbr_stack.lbr_to + i, 0, 0);
> + if (lbr_stack.l...
2017 Sep 25
2
[PATCH v1 4/4] KVM/vmx: enable lbr for the guest
> +static void auto_switch_lbr_msrs(struct vcpu_vmx *vmx)
> +{
> + int i;
> + struct perf_lbr_stack lbr_stack;
> +
> + perf_get_lbr_stack(&lbr_stack);
> +
> + add_atomic_switch_msr(vmx, MSR_LBR_SELECT, 0, 0);
> + add_atomic_switch_msr(vmx, lbr_stack.lbr_tos, 0, 0);
> +
> + for (i = 0; i < lbr_stack.lbr_nr; i++) {
> + add_atomic_switch_msr(vmx, lbr_stack.lbr_from + i, 0, 0);
> + add_atomic_switch_msr(vmx, lbr_stack.lbr_to + i, 0, 0);
> + if (lbr_stack.l...
2017 Sep 25
10
[PATCH v1 0/4] Enable LBR for the guest
This patch series enables the Last Branch Recording feature for the
guest. Instead of trapping each LBR stack MSR access, the MSRs are
passthroughed to the guest. Those MSRs are switched (i.e. load and
saved) on VMExit and VMEntry.
Test:
Try "perf record -b ./test_program" on guest.
Wei Wang (4):
KVM/vmx: re-write the msr auto switch feature
KVM/vmx: auto switch
2017 Sep 25
10
[PATCH v1 0/4] Enable LBR for the guest
This patch series enables the Last Branch Recording feature for the
guest. Instead of trapping each LBR stack MSR access, the MSRs are
passthroughed to the guest. Those MSRs are switched (i.e. load and
saved) on VMExit and VMEntry.
Test:
Try "perf record -b ./test_program" on guest.
Wei Wang (4):
KVM/vmx: re-write the msr auto switch feature
KVM/vmx: auto switch
2017 Sep 25
0
[PATCH v1 4/4] KVM/vmx: enable lbr for the guest
...t_tsc conversion requires 64-bit division. */
@@ -5428,6 +5431,25 @@ static void ept_set_mmio_spte_mask(void)
VMX_EPT_MISCONFIG_WX_VALUE);
}
+static void auto_switch_lbr_msrs(struct vcpu_vmx *vmx)
+{
+ int i;
+ struct perf_lbr_stack lbr_stack;
+
+ perf_get_lbr_stack(&lbr_stack);
+
+ add_atomic_switch_msr(vmx, MSR_LBR_SELECT, 0, 0);
+ add_atomic_switch_msr(vmx, lbr_stack.lbr_tos, 0, 0);
+
+ for (i = 0; i < lbr_stack.lbr_nr; i++) {
+ add_atomic_switch_msr(vmx, lbr_stack.lbr_from + i, 0, 0);
+ add_atomic_switch_msr(vmx, lbr_stack.lbr_to + i, 0, 0);
+ if (lbr_stack.lbr_info)
+ add_atomic_switch...
2017 Sep 25
1
[PATCH v1 4/4] KVM/vmx: enable lbr for the guest
...,6 +5431,25 @@ static void ept_set_mmio_spte_mask(void)
> VMX_EPT_MISCONFIG_WX_VALUE);
> }
>
> +static void auto_switch_lbr_msrs(struct vcpu_vmx *vmx)
> +{
> + int i;
> + struct perf_lbr_stack lbr_stack;
> +
> + perf_get_lbr_stack(&lbr_stack);
> +
> + add_atomic_switch_msr(vmx, MSR_LBR_SELECT, 0, 0);
> + add_atomic_switch_msr(vmx, lbr_stack.lbr_tos, 0, 0);
> +
> + for (i = 0; i < lbr_stack.lbr_nr; i++) {
> + add_atomic_switch_msr(vmx, lbr_stack.lbr_from + i, 0, 0);
> + add_atomic_switch_msr(vmx, lbr_stack.lbr_to + i, 0, 0);
> + if (lbr_stack.l...
2017 Sep 25
1
[PATCH v1 4/4] KVM/vmx: enable lbr for the guest
...,6 +5431,25 @@ static void ept_set_mmio_spte_mask(void)
> VMX_EPT_MISCONFIG_WX_VALUE);
> }
>
> +static void auto_switch_lbr_msrs(struct vcpu_vmx *vmx)
> +{
> + int i;
> + struct perf_lbr_stack lbr_stack;
> +
> + perf_get_lbr_stack(&lbr_stack);
> +
> + add_atomic_switch_msr(vmx, MSR_LBR_SELECT, 0, 0);
> + add_atomic_switch_msr(vmx, lbr_stack.lbr_tos, 0, 0);
> +
> + for (i = 0; i < lbr_stack.lbr_nr; i++) {
> + add_atomic_switch_msr(vmx, lbr_stack.lbr_from + i, 0, 0);
> + add_atomic_switch_msr(vmx, lbr_stack.lbr_to + i, 0, 0);
> + if (lbr_stack.l...
2017 Sep 26
0
[PATCH v1 4/4] KVM/vmx: enable lbr for the guest
On 09/25/2017 10:57 PM, Andi Kleen wrote:
>> +static void auto_switch_lbr_msrs(struct vcpu_vmx *vmx)
>> +{
>> + int i;
>> + struct perf_lbr_stack lbr_stack;
>> +
>> + perf_get_lbr_stack(&lbr_stack);
>> +
>> + add_atomic_switch_msr(vmx, MSR_LBR_SELECT, 0, 0);
>> + add_atomic_switch_msr(vmx, lbr_stack.lbr_tos, 0, 0);
>> +
>> + for (i = 0; i < lbr_stack.lbr_nr; i++) {
>> + add_atomic_switch_msr(vmx, lbr_stack.lbr_from + i, 0, 0);
>> + add_atomic_switch_msr(vmx, lbr_stack.lbr_to + i, 0, 0);
>...
2017 Sep 25
0
[PATCH v1 1/4] KVM/vmx: re-write the msr auto switch feature
...1942,6 +1944,7 @@ static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
m->host[i] = m->host[m->nr];
vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
+ vmcs_write32(VM_EXIT_MSR_STORE_COUNT, m->nr);
}
static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
@@ -1997,7 +2000,7 @@ static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
if (m->guest[i].index == msr)
break;
- if (i == NR_AUTOLOAD_MSRS) {
+ if (i == msr_autoload_count_max) {
printk_once(KERN_WARNING "Not enough msr switch entr...
2017 Sep 25
0
[PATCH v1 2/4] KVM/vmx: auto switch MSR_IA32_DEBUGCTLMSR
...e32(VM_EXIT_MSR_LOAD_COUNT, 0);
vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
vmcs_write64(VM_EXIT_MSR_STORE_ADDR, __pa(vmx->msr_autoload.guest));
- vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
+ add_atomic_switch_msr(vmx, MSR_IA32_DEBUGCTLMSR, 0, 0);
+
if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
@@ -6821,6 +6820,7 @@ static __init int hardware_setup(void)
vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
vmx_disable_interce...
2018 Aug 29
1
Panic / EL6 / KVM / kernel-2.6.32-754.2.1.el6.x86_64
Am 29.08.2018 um 23:46 schrieb Stephen John Smoogen <smooge at gmail.com>:
>
> On Wed, 29 Aug 2018 at 17:41, Leon Fauster via CentOS <centos at centos.org> wrote:
>> Since the update from kernel-2.6.32-754.2.1.el6.x86_64
>> to kernel-2.6.32-754.3.5.el6.x86_64 I can not boot my
>> KVM guests anymore!? The workstation panics immediately!
>>
>> I