search for: add_3r

Displaying 2 results from an estimated 2 matches for "add_3r".

2012 Dec 18
2
[LLVMdev] Issue with instruction decoding / disassembly
...ve run into a problem and I'm not sure of the best way to solve it. With some of the XCore's instruction formats operands are not encoded into bits individually. instead they are combined into a single field using arithmetic operations before being inserted in the instruction. For example: ADD_3r is encoded as: 00010aaaaabbccdd where: aaaaa = op1[3...2] × 9 + op2[3...2] × 3 + op3[3..2] bb = op1[1..0] cc = op2[1..0] dd = op3[1..0] op1 - op3 are all in the range 0-11 and therefore aaaaa is in the range 0 - 26 I managed to get decoding of ADD_3r instructions to work by specifying the value...
2012 Dec 18
0
[LLVMdev] Issue with instruction decoding / disassembly
...o a problem and I'm not sure of the best way to solve it. With some of the XCore's instruction formats operands are not encoded into bits individually. instead they are combined into a single field using arithmetic operations before being inserted in the instruction. For example: > > ADD_3r is encoded as: 00010aaaaabbccdd > > where: > > aaaaa = op1[3...2] × 9 + op2[3...2] × 3 + op3[3..2] > bb = op1[1..0] > cc = op2[1..0] > dd = op3[1..0] > > op1 - op3 are all in the range 0-11 and therefore aaaaa is in the range 0 - 26 > > I managed to get decoding...