search for: add7

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2012 Sep 04
2
[LLVMdev] Fwd: Create superblock in LLVM IR
...en: ; preds = %entry ... br label %if.end if.else: ; preds = %entry ... br label %if.end if.end: ; preds = %if.else, %if.then ... ret i32 %add7 It will be transformed to: define i32 @foo(i32 %a, i32 %b) nounwind uwtable { entry: ... spec.instrinsic.instr.with.label.on.if.else() ... br label %if.end if.else: ; preds = %entry ... br label %if.end if.end:...
2012 Sep 06
0
[LLVMdev] Create superblock in LLVM IR
...; preds = %entry > ... > br label %if.end > if.else: ; preds = %entry > ... > br label %if.end > if.end: ; preds = %if.else, %if.then > ... > ret i32 %add7 > It will be transformed to: > > define i32 @foo(i32 %a, i32 %b) nounwind uwtable { > entry: > ... > spec.instrinsic.instr.with.label.on.if.else() > ... > br label %if.end > if.else: ; preds = %entry...
2012 Mar 01
3
[LLVMdev] Aliasing bug or feature?
...tr inbounds i8* %0, i32 1 %2 = load i8* %arrayidx1, align 1, !tbaa !0 %conv2 = zext i8 %2 to i32 %3 = load i8** @q, align 4, !tbaa !2 <<< Can this load be bypassed by the store below? %4 = load i8* %3, align 1, !tbaa !0 %conv5 = zext i8 %4 to i32 %add = add i32 %conv2, %conv %add7 = add i32 %add, %conv5 %conv8 = trunc i32 %add7 to i8 store i8 %conv8, i8* @s, align 1, !tbaa !0 <<< Can this store bypass the above load? ret void } At the point of enquiry I have the following (lowered) instructions: x3df7900: i32,ch = LDw_GP_V4 0x3df4c70, 0x3df5470<Mem:LD4[@q...
2012 Mar 01
0
[LLVMdev] Aliasing bug or feature?
...2 = load i8* %arrayidx1, align 1, !tbaa !0 >  %conv2 = zext i8 %2 to i32 >  %3 = load i8** @q, align 4, !tbaa !2 <<< Can this load be bypassed by the > store below? >  %4 = load i8* %3, align 1, !tbaa !0 >  %conv5 = zext i8 %4 to i32 >  %add = add i32 %conv2, %conv >  %add7 = add i32 %add, %conv5 >  %conv8 = trunc i32 %add7 to i8 >  store i8 %conv8, i8* @s, align 1, !tbaa !0 <<< Can this store bypass the > above load? Err, are you sure you're asking the right question? Given the loads you're pointing at, you're asking whether &s and...
2012 Sep 17
2
[LLVMdev] Create superblock in LLVM IR
...... >> br label %if.end >> if.else: ; preds = %entry >> ... >> br label %if.end >> if.end: ; preds = %if.else, >> %if.then >> ... >> ret i32 %add7 >> It will be transformed to: >> >> define i32 @foo(i32 %a, i32 %b) nounwind uwtable { >> entry: >> ... >> spec.instrinsic.instr.with.label.on.if.else() >> ... >> br label %if.end >> if.else:...
2014 Sep 18
2
[LLVMdev] [Vectorization] Mis match in code generated
...x2, align 4, !tbaa !1 %add3 = add nsw i32 %add, %2 %arrayidx4 = > getelementptr inbounds i32* %a, i32 3 %3 = load i32* %arrayidx4, align 4, > !tbaa !1 %add5 = add nsw i32 %add3, %3 %arrayidx6 = getelementptr > inbounds i32* %a, i32 4 %4 = load i32* %arrayidx6, align 4, !tbaa !1 > %add7 = add nsw i32 %add5, %4 %arrayidx8 = getelementptr inbounds i32* %a, > i32 5 %5 = load i32* %arrayidx8, align 4, !tbaa !1 %add9 = add nsw i32 > %add7, %5 %arrayidx10 = getelementptr inbounds i32* %a, i32 6 %6 = load > i32* %arrayidx10, align 4, !tbaa !1 %add11 = add nsw i32 %add9, %6...
2014 Sep 19
3
[LLVMdev] [Vectorization] Mis match in code generated
...32* %arrayidx2, align 4, !tbaa !1 %add3 = add nsw i32 %add, %2 %arrayidx4 = getelementptr inbounds i32* %a, i32 3 %3 = load i32* %arrayidx4, align 4, !tbaa !1 %add5 = add nsw i32 %add3, %3 %arrayidx6 = getelementptr inbounds i32* %a, i32 4 %4 = load i32* %arrayidx6, align 4, !tbaa !1 %add7 = add nsw i32 %add5, %4 %arrayidx8 = getelementptr inbounds i32* %a, i32 5 %5 = load i32* %arrayidx8, align 4, !tbaa !1 %add9 = add nsw i32 %add7, %5 %arrayidx10 = getelementptr inbounds i32* %a, i32 6 %6 = load i32* %arrayidx10, align 4, !tbaa !1 %add11 = add nsw i32 %add9, %6 %array...
2012 Sep 17
0
[LLVMdev] Create superblock in LLVM IR
...t; br label %if.end >>> if.else: ; preds = %entry >>> ... >>> br label %if.end >>> if.end: ; preds = %if.else, %if.then >>> ... >>> ret i32 %add7 >>> It will be transformed to: >>> >>> define i32 @foo(i32 %a, i32 %b) nounwind uwtable { >>> entry: >>> ... >>> spec.instrinsic.instr.with.label.on.if.else() >>> ... >>> br label %if.end >>...
2014 Sep 18
2
[LLVMdev] [Vectorization] Mis match in code generated
...= load i32* %arrayidx2, align 4, !tbaa !1 %add3 = add nsw i32 %add, %2 %arrayidx4 = getelementptr inbounds i32* %a, i32 3 %3 = load i32* %arrayidx4, align 4, !tbaa !1 %add5 = add nsw i32 %add3, %3 %arrayidx6 = getelementptr inbounds i32* %a, i32 4 %4 = load i32* %arrayidx6, align 4, !tbaa !1 %add7 = add nsw i32 %add5, %4 %arrayidx8 = getelementptr inbounds i32* %a, i32 5 %5 = load i32* %arrayidx8, align 4, !tbaa !1 %add9 = add nsw i32 %add7, %5 %arrayidx10 = getelementptr inbounds i32* %a, i32 6 %6 = load i32* %arrayidx10, align 4, !tbaa !1 %add11 = add nsw i32 %add9, %6 %arrayidx12 =...
2014 Nov 10
2
[LLVMdev] [Vectorization] Mis match in code generated
...x4 = getelementptr inbounds i32* %a, i32 3 > > > %3 = load i32* %arrayidx4, align 4, !tbaa !1 > > > %add5 = add nsw i32 %add3, %3 > > > %arrayidx6 = getelementptr inbounds i32* %a, i32 4 > > > %4 = load i32* %arrayidx6, align 4, !tbaa !1 > > > %add7 = add nsw i32 %add5, %4 > > > %arrayidx8 = getelementptr inbounds i32* %a, i32 5 > > > %5 = load i32* %arrayidx8, align 4, !tbaa !1 > > > %add9 = add nsw i32 %add7, %5 > > > %arrayidx10 = getelementptr inbounds i32* %a, i32 6 > > > %6 = load i3...
2013 Jun 26
0
[LLVMdev] [llvm] r184698 - Add a flag to defer vectorization into a phase after the inliner and its
Sent from my iPhone... On Jun 25, 2013, at 8:14 AM, Hal Finkel <hfinkel at anl.gov> wrote: > ----- Original Message ----- >> >> >> >> On Jun 24, 2013, at 4:24 PM, Hal Finkel < hfinkel at anl.gov > wrote: >> >> >> >> >> Indvars should ideally preserve NSW flags whenever possible. However, >> we don't want to
2013 Nov 11
2
[LLVMdev] What's the Alias Analysis does clang use ?
...%mul = fmul double %conv, 6.700000e-01 %9 = load float* %y, align 4 %conv3 = fpext float %9 to double %mul4 = fmul double %conv3, 1.700000e-01 %add = fadd double %mul, %mul4 %10 = load float* %z, align 4 %conv5 = fpext float %10 to double %mul6 = fmul double %conv5, 1.600000e-01 %add7 = fadd double %add, %mul6 %conv8 = fptrunc double %add7 to float store float %conv8, float* %res, align 4 %11 = load float* %res, align 4 %12 = load i32* %i, align 4 %idxprom = sext i32 %12 to i64 %arrayidx9 = getelementptr inbounds float* %3, i64 %idxprom store float %11, float* %arr...
2013 Jun 25
2
[LLVMdev] [llvm] r184698 - Add a flag to defer vectorization into a phase after the inliner and its
----- Original Message ----- > > > > On Jun 24, 2013, at 4:24 PM, Hal Finkel < hfinkel at anl.gov > wrote: > > > > > Indvars should ideally preserve NSW flags whenever possible. However, > we don't want to rely on SCEV to preserve them. SCEV expressions are > implicitly reassociated and uniqued in a flow-insensitive universe > independent of the
2012 Mar 01
0
[LLVMdev] problem with inlining pass
Hi Jochen, > My llvm version is 3.0 release. > I have a module generated by clang. When I optimize it, I first add an > inlining pass (llvm::createFunctionInliningPass), then these passes: > - own FunctionPass > - llvm::createPromoteMemoryToRegisterPass > - llvm::createInstructionCombiningPass > - llvm::createDeadInstEliminationPass > - llvm::createDeadStoreEliminationPass
2013 Nov 12
0
[LLVMdev] What's the Alias Analysis does clang use ?
...onv, 6.700000e-01 > %9 = load float* %y, align 4 > %conv3 = fpext float %9 to double > %mul4 = fmul double %conv3, 1.700000e-01 > %add = fadd double %mul, %mul4 > %10 = load float* %z, align 4 > %conv5 = fpext float %10 to double > %mul6 = fmul double %conv5, 1.600000e-01 > %add7 = fadd double %add, %mul6 > %conv8 = fptrunc double %add7 to float > store float %conv8, float* %res, align 4 > %11 = load float* %res, align 4 > %12 = load i32* %i, align 4 > %idxprom = sext i32 %12 to i64 > %arrayidx9 = getelementptr inbounds float* %3, i64 %idxprom > store f...
2012 Feb 29
2
[LLVMdev] problem with inlining pass
Hi! My llvm version is 3.0 release. I have a module generated by clang. When I optimize it, I first add an inlining pass (llvm::createFunctionInliningPass), then these passes: - own FunctionPass - llvm::createPromoteMemoryToRegisterPass - llvm::createInstructionCombiningPass - llvm::createDeadInstEliminationPass - llvm::createDeadStoreEliminationPass - new llvm::DominatorTree() - new
2016 May 05
6
Code which should exit 1 is exiting 0
I have IR at https://ghostbin.com/paste/daxv5 <https://ghostbin.com/paste/daxv5> which is meant to exit 1, but it is always exiting 0. I'm using it as a template for checking if two functions @test1 and @test2 are equivalent by checking against the exhaustive possible i16 values. For this particular example it should be enough to know that for certain i16, @test1 and @test2 are *not*
2011 Dec 02
5
[LLVMdev] [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
...= load double* %arrayidx3, align 8 > + %arrayidx4 = getelementptr inbounds double* %b, i64 1 > + %i4 = load double* %arrayidx4, align 8 > + %mul5 = fmul double %i3, %i4 > + %arrayidx6 = getelementptr inbounds double* %c, i64 1 > + %i5 = load double* %arrayidx6, align 8 > + %add7 = fadd double %mul5, %i5 > + %mul9 = fmul double %add, %i1 > + %add11 = fadd double %mul9, %i2 > + %mul13 = fmul double %add7, %i4 > + %add15 = fadd double %mul13, %i5 > + %mul16 = fmul double %add11, %add15 > + ret double %mul16 > +; CHECK: @test1 > +; CHECK:<2 x d...
2011 Dec 14
0
[LLVMdev] [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
...ign 8 > > + %arrayidx4 = getelementptr inbounds double* %b, i64 1 > > + %i4 = load double* %arrayidx4, align 8 > > + %mul5 = fmul double %i3, %i4 > > + %arrayidx6 = getelementptr inbounds double* %c, i64 1 > > + %i5 = load double* %arrayidx6, align 8 > > + %add7 = fadd double %mul5, %i5 > > + %mul9 = fmul double %add, %i1 > > + %add11 = fadd double %mul9, %i2 > > + %mul13 = fmul double %add7, %i4 > > + %add15 = fadd double %mul13, %i5 > > + %mul16 = fmul double %add11, %add15 > > + ret double %mul16 > > +; CH...
2011 Nov 23
0
[LLVMdev] [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
On Mon, 2011-11-21 at 21:22 -0600, Hal Finkel wrote: > On Mon, 2011-11-21 at 11:55 -0600, Hal Finkel wrote: > > Tobias, > > > > I've attached an updated patch. It contains a few bug fixes and many > > (refactoring and coding-convention) changes inspired by your comments. > > > > I'm currently trying to fix the bug responsible for causing a compile