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2014 Sep 02
2
[LLVMdev] Instruction Selection sanity check
Hi,
I am working on a new back-end for LLVM. This architecture has two register
types, data(A) and accumulator(B).
A registers are i32 where as B registers are i64. This is causing me some
headaches, as far as I can tell, it's not really possible to mix the two
using tablegen?
In the hardware, every instruction can either take an A register or a B
register, in tablegen (as far as I can