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add32ri
2013 Mar 20
2
[LLVMdev] Strange spill behaviour
...e being spilled, I assume the fault lies in my
tablegen definitions (relevant ones reproduced below) :
let isCommutable=1 in
{
def ADD32rrr : M819Inst<(outs GR32:$dst),(ins GR32:$src1,
GR32:$src2),"ADD.L\t{$dst,$src1 + $src2}",[(set GR32:$dst, (add GR32:$src1,
GR32:$src2))]>;
}
def ADD32rri : M819Inst<(outs GR32:$dst),(ins GR32:$src1,
i32imm:$src2),"ADD.L\t{$dst,$src1 + $src2}",[(set GR32:$dst, (add
GR32:$src1, imm:$src2))]>;
def SUB32rrr : M819Inst<(outs GR32:$dst),(ins GR32:$src1,
GR32:$src2),"SUB.L\t{$dst,$src1 - $src2}",[(set GR32:$dst, (sub GR32:$src...