search for: add32rm

...s on X86 instructions, which would require identifying memory reference instructions. In the X86 back end instructions, memory addresses consist of a set of five operands. The offset to the start of the five operands depends on the format of the instruction. For instance, the instructions ADC32rm, ADD32rm, AND32rm, ANDN32rm, CMOVA32rm, CMOVAE32rm, CMOVB32rm, et al. all have a 32 bit memory address set starting at operand 2. There does not seem to be any way to obtain the offset to the start of a memory reference in an X86 MachineInstr. Tablegen code is able to determine the offset when it generate...

...ptr i32* %p, i32 17 %r = load i32* %q %s = add i32 %r, 10 ret i32 %s } The llc -march=x86 -print-machineinstrs output looks like this: : 0x8a99fc8, LLVM BB @0x8a94998, ID#0: %reg1024 = MOV32ri 10 SV:0 %reg1025 = MOV32rm <fi#-1>, 1, %NOREG, 0 SV:1[??] %reg1026 = ADD32rm %reg1024, %reg1025, 1, %NOREG, 68 SV:1[q] %EAX = MOV32rr %reg1026 SV:0 RET SV:0 (For those following along, the SV:1[??] and SV:1[q] are the new parts here). For the [??], it looks like the IsFrameIndex isn't getting set for the first instruction there. A few quick comments o...

Dan Gohman wrote: > I tried out your patch on x86 and it didn't appear to need any special changes. it might be needed to look at the addressing modes of a load/store to get the right offset. but i think it should work, if the lowering does not rewrite loads/stores into custom DAG nodes. > For the [??], it looks like the IsFrameIndex isn't getting set for the first > instruction

Hi all, Memory fold tables: Two way mapping of each register-form instruction to its corresponding memory-form instruction. E.g. Mapping 'X86::ADD32rr' to 'X86::ADD32rm'. Few months ago I started an effort to auto-generate the X86 memory folding tables currently held under lib/Target/X86/X86InstInfo.cpp as huge manually-maintained static arrays. Automating the tables would reduce the maintenance burden for developers to repeatedly update them with every new (...

hi, i know it took a while, but here is a patch that adds a list of source values to machine instructions. i modified the DAGISelEmiter to automatically catch regular loads/stores. custom instructions and loads/stores rewritten by the lowering pass are not automatically captured. during the instruction selection a source value operand is added to the DAG for patterns matching a load/store.

hi, Florian Brandner wrote: > Dan Gohman wrote: >> On Wed, May 23, 2007 at 12:23:38AM -0700, Chris Lattner wrote: >>> Right. The original Value*'s are preserved in the DAG, but dropped when >>> MachineInstrs are created. We could add a machineoperand to capture this >>> Value* if desired. >> Another benefit of keeping the original Value*'s