search for: adcl

...%edx movl 4(%edi), %ebx movl 60(%eax), %ecx movl %ecx, 52(%esp) # 4-byte Spill movl 56(%eax), %ecx movl %ecx, 48(%esp) # 4-byte Spill addl (%eax), %edx movl %edx, 24(%esp) # 4-byte Spill adcl 4(%eax), %ebx movl %ebx, 20(%esp) # 4-byte Spill adcl 8(%eax), %esi movl %esi, 16(%esp) # 4-byte Spill movl 52(%eax), %ecx movl %ecx, 40(%esp) # 4-byte Spill movl 48(%eax), %ecx movl %ecx, 36(...

...fine i1 @cc(i32 %x, i32 %y) { %xx = zext i32 %x to i33 %yy = zext i32 %y to i33 %s = add i33 %xx, %yy %tmp = lshr i33 %s, 32 %b = trunc i33 %tmp to i1 ret i1 %b } codegens (on x86-32) to cc: xorl %eax, %eax movl 4(%esp), %ecx addl 8(%esp), %ecx adcl $0, %eax andl $1, %eax ret which uses the condition code as desired. Pity about the redundant andl $1, %eax! Ciao, Duncan.

...d Reload addsd 40(%esp), %xmm2 # 8-byte Folded Reload addsd 48(%esp), %xmm2 # 8-byte Folded Reload addsd 56(%esp), %xmm2 # 8-byte Folded Reload addsd 64(%esp), %xmm2 # 8-byte Folded Reload addsd 72(%esp), %xmm2 # 8-byte Folded Reload addsd %xmm2, %xmm0 adcl $0, %esi cmpl %eax, %edi movl %edi, %ebx jne .LBB1_2 .LBB1_3: # %._crit_edge movsd %xmm0, 80(%esp) fldl 80(%esp) addl $88, %esp popl %esi popl %edi popl %ebx ret .Ltmp20: .size foo, .Ltmp20-foo .Ltmp21: .cfi_endproc .Leh_func_end1: ====== Output B ======...

...d Reload addsd 40(%esp), %xmm2 # 8-byte Folded Reload addsd 48(%esp), %xmm2 # 8-byte Folded Reload addsd 56(%esp), %xmm2 # 8-byte Folded Reload addsd 64(%esp), %xmm2 # 8-byte Folded Reload addsd 72(%esp), %xmm2 # 8-byte Folded Reload addsd %xmm2, %xmm0 adcl $0, %esi cmpl %eax, %edi movl %edi, %ebx jne .LBB1_2 .LBB1_3: # %._crit_edge movsd %xmm0, 80(%esp) fldl 80(%esp) addl $88, %esp popl %esi popl %edi popl %ebx ret .Ltmp20: .size foo, .Ltmp20-foo .Ltmp21: .cfi_endproc .Leh_func_end1: ====== Output B ======...

This patches add support for dynamic sectors to GPT MBR code. First 3 patches are trick and optimizations to gain some space for the forth patch. I have a modified version of SeaBIOS, some code and some script o test it I'll send on a different mail.

On Wed, 26 Mar 2008, Jonathan S. Shapiro wrote: > I want to background process this for a bit, but it would be helpful to > discuss some approaches first. > > There would appear to be three approaches: > > 1. Introduce a CC register class into the IR. This seems to be a > fairly major overhaul. > > 2. Introduce a set of scalar and fp computation quasi-instructions

...t; %yy = zext i32 %y to i33 > %s = add i33 %xx, %yy > %tmp = lshr i33 %s, 32 > %b = trunc i33 %tmp to i1 > ret i1 %b > } > > codegens (on x86-32) to > > cc: > xorl %eax, %eax > movl 4(%esp), %ecx > addl 8(%esp), %ecx > adcl $0, %eax > andl $1, %eax > ret > > which uses the condition code as desired. Pity about the > redundant andl $1, %eax! > > Ciao, > > Duncan. > -Chris -- http://nondot.org/sabre/ http://llvm.org/

On Tue, 2008-03-25 at 21:18 -0700, Chris Lattner wrote: > On Mar 25, 2008, at 8:25 PM, Jonathan S. Shapiro wrote: > > > In looking at the LLVM reference manual, it is conspicuous that (a) > > the > > IR does not define condition codes, and (b) the IR does not define > > opcodes that return condition results in addition to their > > computational > >

..."isolinux.bin missing or corrupt.\r\n" boot_failure: int $0x18 /* Boot failure */ die: hlt jmp die /* * read_sector: read a single sector pointed to by %eax to %es:%bx. * CF is set on error. All registers saved. */ read_sector: pushal xorl %edx, %edx addl (partoffset), %eax adcl (partoffset+4), %edx pushl %edx /* MSW of LBA */ pushl %eax /* LSW of LBA */ pushw %es /* Buffer segment */ pushw %bx /* Buffer offset */ pushw $1 /* Sector count */ pushw $16 /* Size of packet */ movw %sp, %si /* This chunk is skipped if we have ebios */ /* Do not clobber %eax before thi...

This set of patches add some support for sector size >512. Currently it fixes extlinux, MBR for GPT and ext partitions. Other code is unaffected. This set of patches has been tested on a read Dell machine running a beta firmware.