Displaying 1 result from an estimated 1 matches for "active_vscale".
2018 Jun 12
3
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
Hi Robin,
responses inline.
-Graham
> On 11 Jun 2018, at 16:47, Robin Kruppe <robin.kruppe at gmail.com> wrote:
>
> Hi Graham,
> Hi David,
>
> glad to hear other people are thinking about RVV codegen!
>
> On 7 June 2018 at 18:10, Graham Hunter <Graham.Hunter at arm.com> wrote:
>>
>> Hi,
>>
>>> On 6 Jun 2018, at 17:36, David A.