Displaying 3 results from an estimated 3 matches for "acr_r352_wpr_is_set".
2019 Sep 17
2
[PATCH 03/11] drm/nouveau: secboot: Read WPR configuration from GPU registers
...e);
> +
> + /* read base address */
> + value = nvkm_rd32(device, 0x100cd4);
> + base = (u64)(value >> 4) << 12;
> +
> + /* read limit */
> + value = nvkm_rd32(device, 0x100cd4);
> + limit = (u64)(value >> 4) << 12;
acr_r352_wpr_is_set() does a similar readout to confirm the HS
firmware did its job on dGPU, perhaps this part of it could be
factored out into a function that could be used in both places?
> +
> + /*
> + * The upper address of the WPR seems to be computed wrongly and is
> + * actually...
2019 Sep 17
0
[PATCH 03/11] drm/nouveau: secboot: Read WPR configuration from GPU registers
...e address */
> > + value = nvkm_rd32(device, 0x100cd4);
> > + base = (u64)(value >> 4) << 12;
> > +
> > + /* read limit */
> > + value = nvkm_rd32(device, 0x100cd4);
> > + limit = (u64)(value >> 4) << 12;
> acr_r352_wpr_is_set() does a similar readout to confirm the HS
> firmware did its job on dGPU, perhaps this part of it could be
> factored out into a function that could be used in both places?
I hadn't seen that function. It looks to me like these are now both
doing exactly the same thing. The acr_r352_wpr...
2019 Sep 16
15
[PATCH 00/11] drm/nouveau: Enable GP10B by default
From: Thierry Reding <treding at nvidia.com>
Hi,
the GPU on Jetson TX2 (GP10B) does not work properly on all devices. Why
exactly is not clear, but there are slight differences between the SKUs
that were tested. It turns out that the biggest issue is that on some
devices (e.g. the one that I have), pulsing the GPU reset twice as is
done in the current code (once as part of the power-ungate