search for: acr_r352_ls_func

...boot/acr_r352.c @@ -414,6 +414,20 @@ acr_r352_ls_write_wpr(struct acr_r352 *acr, struct list_head *imgs, { struct ls_ucode_img *_img; u32 pos = 0; + u32 max_desc_size = 0; + u8 *gdesc; + + /* Figure out how large we need gdesc to be. */ + list_for_each_entry(_img, imgs, node) { + const struct acr_r352_ls_func *ls_func = + acr->func->ls_func[_img->falcon_id]; + + max_desc_size = max(max_desc_size, ls_func->bl_desc_size); + } + + gdesc = kmalloc(max_desc_size, GFP_KERNEL); + if (!gdesc) + return -ENOMEM; nvkm_kmap(wpr_blob); @@ -421,7 +435,6 @@ acr_r352_ls_write_wpr(struct acr_...

...ead *imgs, > { > struct ls_ucode_img *_img; > u32 pos = 0; > + u32 max_desc_size = 0; > + u8 *gdesc; > + > + /* Figure out how large we need gdesc to be. */ > + list_for_each_entry(_img, imgs, node) { > + const struct acr_r352_ls_func *ls_func = > + acr->func->ls_func[_img->falcon_id]; > + > + max_desc_size = max(max_desc_size, ls_func->bl_desc_size); > + } > + > + gdesc = kmalloc(max_desc_size, GFP_KERNEL); > + if (!gdesc)...

...r352.c b/drm/nouveau/nvkm/subdev/secboot/acr_r352.c index b350e107eff0..cdba9ffc5bbe 100644 --- a/drm/nouveau/nvkm/subdev/secboot/acr_r352.c +++ b/drm/nouveau/nvkm/subdev/secboot/acr_r352.c @@ -214,12 +214,6 @@ ls_ucode_img_fill_headers(struct acr_r352 *acr, struct ls_ucode_img *img, const struct acr_r352_ls_func *func = acr->func->ls_func[img->falcon_id]; - if (img->ucode_header) { - nvkm_fatal(acr->base.subdev, - "images withough loader are not supported yet!\n"); - return offset; - } - /* Fill WPR header */ whdr->falcon_id = img->falcon_id; whdr-&gt...

...struct ls_ucode_img *_img; >> u32 pos = 0; >> + u32 max_desc_size = 0; >> + u8 *gdesc; >> + >> + /* Figure out how large we need gdesc to be. */ >> + list_for_each_entry(_img, imgs, node) { >> + const struct acr_r352_ls_func *ls_func = >> + acr->func->ls_func[_img->falcon_id]; >> + >> + max_desc_size = max(max_desc_size, ls_func->bl_desc_size); >> + } >> + >> + gdesc = kmalloc(max_desc_size, GFP_KERNEL);...

...eau/nvkm/subdev/secboot/acr_r352.c index 4fd4cfe..7af971d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c @@ -1088,7 +1088,7 @@ acr_r352_ls_gpccs_func_0 = { .lhdr_flags = LSF_FLAG_FORCE_PRIV_LOAD, }; -const struct acr_r352_ls_func +static const struct acr_r352_ls_func acr_r352_ls_gpccs_func = { .load = acr_ls_ucode_load_gpccs, .version_max = 0, -- 2.7.4

...g; >>> u32 pos = 0; >>> + u32 max_desc_size = 0; >>> + u8 *gdesc; >>> + >>> + /* Figure out how large we need gdesc to be. */ >>> + list_for_each_entry(_img, imgs, node) { >>> + const struct acr_r352_ls_func *ls_func = >>> + acr->func->ls_func[_img->falcon_id]; >>> + >>> + max_desc_size = max(max_desc_size, ls_func->bl_desc_size); >>> + } >>> + >>> + gdesc = kmalloc(max_...

..._img_desc *desc = &img->ucode_desc; + struct ls_ucode_img *_img = &img->base; + struct acr_r352_lsf_wpr_header *whdr = &img->wpr_header; + struct acr_r352_lsf_lsb_header *lhdr = &img->lsb_header; + struct ls_ucode_img_desc *desc = &_img->ucode_desc; const struct acr_r352_ls_func *func = - acr->func->ls_func[img->falcon_id]; + acr->func->ls_func[_img->falcon_id]; /* Fill WPR header */ - whdr->falcon_id = img->falcon_id; + whdr->falcon_id = _img->falcon_id; whdr->bootstrap_owner = acr->base.func->boot_falcon; whd...

...vkm_gpuobj *wpr_blob, u32 wpr_addr) { struct ls_ucode_img *img; @@ -354,7 +323,7 @@ ls_ucode_mgr_write_wpr(struct acr_r352 *acr, struct ls_ucode_mgr *mgr, nvkm_kmap(wpr_blob); - list_for_each_entry(img, &mgr->img_list, node) { + list_for_each_entry(img, imgs, node) { const struct acr_r352_ls_func *ls_func = acr->func->ls_func[img->falcon_id]; u8 gdesc[ls_func->bl_desc_size]; @@ -400,11 +369,14 @@ acr_r352_prepare_ls_blob(struct acr_r352 *acr, u64 wpr_addr, u32 wpr_size, unsigned long managed_falcons) { const struct nvkm_subdev *subdev = acr->base.subdev;...

Sending things in a smaller chunks since it makes their reviewing easier. This part part 2/3 of the secboot refactoring/PMU command support patch series. Part 1 was the new falcon library which should be merged soon now. This series is mainly a refactoring/sanitization of the existing secure boot code. It does not add new features (part 3 will). Secure boot handling is now separated by NVIDIA

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,

GP10B is the chip used in Tegra X2 SoCs. This patchset adds support for its base engines after reworking secboot a bit to accomodate its calling convention better. This patchset has been tested rendering simple off-screen buffers using Mesa and yielded the expected result. Alexandre Courbot (15): secboot: allow to boot multiple falcons secboot: pass instance to LS firmware loaders secboot: